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radeonsi: fix DRM version checks for amdgpu DRM 3.0.0

This commit is contained in:
Marek Olšák 2015-04-16 20:35:27 +02:00
parent e7fc664b91
commit 8ba70e0a74
5 changed files with 19 additions and 11 deletions
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6
src/gallium/drivers/radeon/r600_buffer_common.c
View File

@ -121,7 +121,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
/* Older kernels didn't always flush the HDP cache before
* CS execution
*/
if (rscreen->info.drm_minor < 40) {
if (rscreen->info.drm_major == 2 &&
rscreen->info.drm_minor < 40) {
res->domains = RADEON_DOMAIN_GTT;
flags |= RADEON_FLAG_GTT_WC;
break;
@ -147,7 +148,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
* Write-combined CPU mappings are fine, the kernel ensures all CPU
* writes finish before the GPU executes a command stream.
*/
if (rscreen->info.drm_minor < 40)
if (rscreen->info.drm_major == 2 &&
rscreen->info.drm_minor < 40)
res->domains = RADEON_DOMAIN_GTT;
else if (res->domains & RADEON_DOMAIN_VRAM)
flags |= RADEON_FLAG_CPU_ACCESS;

4
src/gallium/drivers/radeon/r600_pipe_common.c
View File

@ -928,7 +928,9 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
pipe_mutex_init(rscreen->aux_context_lock);
pipe_mutex_init(rscreen->gpu_load_mutex);
if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
rscreen->info.drm_major == 3) &&
(rscreen->debug_flags & DBG_TRACE_CS)) {
rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
PIPE_BIND_CUSTOM,
PIPE_USAGE_STAGING,

8
src/gallium/drivers/radeon/r600_texture.c
View File

@ -490,7 +490,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
unsigned num_pipes = rscreen->tiling_info.num_channels;
if (rscreen->chip_class <= EVERGREEN &&
rscreen->info.drm_minor < 26)
rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
return 0;
/* HW bug on R6xx. */
@ -502,7 +502,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
/* HTILE is broken with 1D tiling on old kernels and CIK. */
if (rscreen->chip_class >= CIK &&
rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
rscreen->info.drm_minor < 38)
rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
return 0;
switch (num_pipes) {
@ -1261,7 +1261,9 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
/* fast color clear with 1D tiling doesn't work on old kernels and CIK */
if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
rctx->chip_class >= CIK && rctx->screen->info.drm_minor < 38) {
rctx->chip_class >= CIK &&
rctx->screen->info.drm_major == 2 &&
rctx->screen->info.drm_minor < 38) {
continue;
}

4
src/gallium/drivers/radeonsi/si_pipe.c
View File

@ -271,7 +271,9 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_MULTISAMPLE:
/* 2D tiling on CIK is supported since DRM 2.35.0 */
return sscreen->b.chip_class < CIK ||
sscreen->b.info.drm_minor >= 35;
(sscreen->b.info.drm_major == 2 &&
sscreen->b.info.drm_minor >= 35) ||
sscreen->b.info.drm_major == 3;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return R600_MAP_BUFFER_ALIGNMENT;

8
src/gallium/drivers/radeonsi/si_state.c
View File

@ -1178,7 +1178,9 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen,
int first_non_void)
{
struct si_screen *sscreen = (struct si_screen*)screen;
bool enable_compressed_formats = sscreen->b.info.drm_minor >= 31;
bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
sscreen->b.info.drm_minor >= 31) ||
sscreen->b.info.drm_major == 3;
boolean uniform = TRUE;
int i;
@ -1626,7 +1628,6 @@ boolean si_is_format_supported(struct pipe_screen *screen,
unsigned sample_count,
unsigned usage)
{
struct si_screen *sscreen = (struct si_screen *)screen;
unsigned retval = 0;
if (target >= PIPE_MAX_TEXTURE_TYPES) {
@ -1638,8 +1639,7 @@ boolean si_is_format_supported(struct pipe_screen *screen,
return FALSE;
if (sample_count > 1) {
/* 2D tiling on CIK is supported since DRM 2.35.0 */
if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
return FALSE;
switch (sample_count) {