intel/common: Add unit tests for gen_mi_builder
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Jason Ekstrand
parent
2f7fcd103e
commit
8b8deeca78
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@ -276,6 +276,12 @@ option(
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value : false,
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description : 'Build unit tests. Currently this will build *all* unit tests, which may build more than expected.'
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)
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option(
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'install-intel-gpu-tests',
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type : 'boolean',
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value : false,
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description : 'Build and install Intel unit tests which require the GPU. This option is for developers and the Intel CI system only.'
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)
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option(
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'selinux',
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type : 'boolean',
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@ -43,3 +43,23 @@ libintel_common = static_library(
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link_with : [libisl],
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dependencies : [dep_expat, dep_libdrm, dep_thread, idep_genxml],
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)
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install_intel_gpu_tests = get_option('install-intel-gpu-tests')
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if install_intel_gpu_tests
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foreach g : [['70', 'gen7'], ['75', 'hsw'], ['80', 'gen8'],
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['90', 'gen9'], ['110', 'gen11']]
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executable(
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'intel_@0@_mi_builder_test'.format(g[1]),
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files('tests/gen_mi_builder_test.cpp'),
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cpp_args : [
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cpp_vis_args, cpp_msvc_compat_args,
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'-DGEN_VERSIONx10=@0@'.format(g[0])
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],
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include_directories : [inc_common, inc_intel],
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link_with : [libintel_dev, libmesa_util],
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dependencies : [dep_libdrm, dep_thread, idep_gtest, idep_genxml],
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install : install_intel_gpu_tests,
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)
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endforeach
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endif
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@ -0,0 +1,641 @@
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/*
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* Copyright © 2019 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <fcntl.h>
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#include <string.h>
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#include <xf86drm.h>
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#include <gtest/gtest.h>
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#include "dev/gen_device_info.h"
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#include "drm-uapi/i915_drm.h"
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#include "genxml/gen_macros.h"
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#include "util/macros.h"
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class gen_mi_builder_test;
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struct address {
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uint32_t gem_handle;
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uint32_t offset;
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};
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#define __gen_address_type struct address
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#define __gen_user_data ::gen_mi_builder_test
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uint64_t __gen_combine_address(gen_mi_builder_test *test, void *location,
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struct address addr, uint32_t delta);
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void * __gen_get_batch_dwords(gen_mi_builder_test *test, unsigned num_dwords);
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struct address
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__gen_address_offset(address addr, uint64_t offset)
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{
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addr.offset += offset;
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return addr;
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}
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#if GEN_GEN >= 8 || GEN_IS_HASWELL
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#define RSVD_TEMP_REG 0x2678 /* MI_ALU_REG15 */
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#else
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#define RSVD_TEMP_REG 0x2430 /* GEN7_3DPRIM_START_VERTEX */
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#endif
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#define GEN_MI_BUILDER_NUM_ALLOC_GPRS 15
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#define INPUT_DATA_OFFSET 0
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#define OUTPUT_DATA_OFFSET 2048
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#include "genxml/genX_pack.h"
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#include "gen_mi_builder.h"
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#include <vector>
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class gen_mi_builder_test : public ::testing::Test {
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public:
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gen_mi_builder_test();
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~gen_mi_builder_test();
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void SetUp();
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void *emit_dwords(int num_dwords);
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void submit_batch();
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inline address in_addr(uint32_t offset)
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{
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address addr;
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addr.gem_handle = data_bo_handle;
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addr.offset = INPUT_DATA_OFFSET + offset;
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return addr;
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}
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inline address out_addr(uint32_t offset)
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{
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address addr;
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addr.gem_handle = data_bo_handle;
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addr.offset = OUTPUT_DATA_OFFSET + offset;
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return addr;
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}
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inline gen_mi_value in_mem64(uint32_t offset)
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{
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return gen_mi_mem64(in_addr(offset));
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}
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inline gen_mi_value in_mem32(uint32_t offset)
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{
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return gen_mi_mem32(in_addr(offset));
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}
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inline gen_mi_value out_mem64(uint32_t offset)
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{
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return gen_mi_mem64(out_addr(offset));
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}
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inline gen_mi_value out_mem32(uint32_t offset)
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{
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return gen_mi_mem32(out_addr(offset));
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}
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int fd;
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gen_device_info devinfo;
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uint32_t batch_bo_handle;
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uint32_t batch_offset;
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void *batch_map;
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std::vector<drm_i915_gem_relocation_entry> relocs;
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uint32_t data_bo_handle;
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void *data_map;
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char *input;
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char *output;
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uint64_t canary;
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gen_mi_builder b;
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};
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gen_mi_builder_test::gen_mi_builder_test() :
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fd(-1)
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{ }
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gen_mi_builder_test::~gen_mi_builder_test()
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{
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close(fd);
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}
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// 1 MB of batch should be enough for anyone, right?
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#define BATCH_BO_SIZE (256 * 4096)
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#define DATA_BO_SIZE 4096
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void
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gen_mi_builder_test::SetUp()
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{
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drmDevicePtr devices[8];
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int max_devices = drmGetDevices2(0, devices, 8);
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int i;
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for (i = 0; i < max_devices; i++) {
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if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
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devices[i]->bustype == DRM_BUS_PCI &&
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devices[i]->deviceinfo.pci->vendor_id == 0x8086) {
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fd = open(devices[i]->nodes[DRM_NODE_RENDER], O_RDWR | O_CLOEXEC);
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if (fd < 0)
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continue;
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/* We don't really need to do this when running on hardware because
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* we can just pull it from the drmDevice. However, without doing
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* this, intel_dump_gpu gets a bit of heartburn and we can't use the
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* --device option with it.
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*/
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int device_id;
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drm_i915_getparam getparam = drm_i915_getparam();
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getparam.param = I915_PARAM_CHIPSET_ID;
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getparam.value = &device_id;
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ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GETPARAM,
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(void *)&getparam), 0) << strerror(errno);
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ASSERT_TRUE(gen_get_device_info(device_id, &devinfo));
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if (devinfo.gen != GEN_GEN || devinfo.is_haswell != GEN_IS_HASWELL) {
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close(fd);
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fd = -1;
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continue;
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}
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/* Found a device! */
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break;
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}
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}
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ASSERT_TRUE(i < max_devices) << "Failed to find a DRM device";
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// Create the batch buffer
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drm_i915_gem_create gem_create = drm_i915_gem_create();
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gem_create.size = BATCH_BO_SIZE;
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ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE,
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(void *)&gem_create), 0) << strerror(errno);
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batch_bo_handle = gem_create.handle;
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drm_i915_gem_caching gem_caching = drm_i915_gem_caching();
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gem_caching.handle = batch_bo_handle;
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gem_caching.caching = I915_CACHING_CACHED;
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ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_SET_CACHING,
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(void *)&gem_caching), 0) << strerror(errno);
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drm_i915_gem_mmap gem_mmap = drm_i915_gem_mmap();
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gem_mmap.handle = batch_bo_handle;
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gem_mmap.offset = 0;
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gem_mmap.size = BATCH_BO_SIZE;
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gem_mmap.flags = 0;
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ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP,
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(void *)&gem_mmap), 0) << strerror(errno);
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batch_map = (void *)(uintptr_t)gem_mmap.addr_ptr;
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// Start the batch at zero
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batch_offset = 0;
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// Create the data buffer
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gem_create = drm_i915_gem_create();
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gem_create.size = DATA_BO_SIZE;
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ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE,
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(void *)&gem_create), 0) << strerror(errno);
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data_bo_handle = gem_create.handle;
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gem_caching = drm_i915_gem_caching();
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gem_caching.handle = data_bo_handle;
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gem_caching.caching = I915_CACHING_CACHED;
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ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_SET_CACHING,
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(void *)&gem_caching), 0) << strerror(errno);
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gem_mmap = drm_i915_gem_mmap();
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gem_mmap.handle = data_bo_handle;
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gem_mmap.offset = 0;
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gem_mmap.size = DATA_BO_SIZE;
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gem_mmap.flags = 0;
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ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP,
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(void *)&gem_mmap), 0) << strerror(errno);
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data_map = (void *)(uintptr_t)gem_mmap.addr_ptr;
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input = (char *)data_map + INPUT_DATA_OFFSET;
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output = (char *)data_map + OUTPUT_DATA_OFFSET;
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// Fill the test data with garbage
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memset(data_map, 139, DATA_BO_SIZE);
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memset(&canary, 139, sizeof(canary));
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gen_mi_builder_init(&b, this);
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}
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void *
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gen_mi_builder_test::emit_dwords(int num_dwords)
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{
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void *ptr = (void *)((char *)batch_map + batch_offset);
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batch_offset += num_dwords * 4;
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assert(batch_offset < BATCH_BO_SIZE);
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return ptr;
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}
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void
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gen_mi_builder_test::submit_batch()
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{
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gen_mi_builder_emit(&b, GENX(MI_BATCH_BUFFER_END), bbe);
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// Round batch up to an even number of dwords.
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if (batch_offset & 4)
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gen_mi_builder_emit(&b, GENX(MI_NOOP), noop);
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drm_i915_gem_exec_object2 objects[2];
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memset(objects, 0, sizeof(objects));
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objects[0].handle = data_bo_handle;
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objects[0].relocation_count = 0;
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objects[0].relocs_ptr = 0;
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objects[0].flags = EXEC_OBJECT_WRITE;
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objects[0].offset = -1;
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if (GEN_GEN >= 8)
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objects[0].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
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objects[1].handle = batch_bo_handle;
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objects[1].relocation_count = relocs.size();
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objects[1].relocs_ptr = (uintptr_t)(void *)&relocs[0];
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objects[1].flags = 0;
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objects[1].offset = -1;
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if (GEN_GEN >= 8)
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objects[1].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
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drm_i915_gem_execbuffer2 execbuf = drm_i915_gem_execbuffer2();
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execbuf.buffers_ptr = (uintptr_t)(void *)objects;
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execbuf.buffer_count = 2;
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execbuf.batch_start_offset = 0;
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execbuf.batch_len = batch_offset;
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execbuf.flags = I915_EXEC_HANDLE_LUT | I915_EXEC_RENDER;
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ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2,
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(void *)&execbuf), 0) << strerror(errno);
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drm_i915_gem_wait gem_wait = drm_i915_gem_wait();
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gem_wait.bo_handle = batch_bo_handle;
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gem_wait.timeout_ns = INT64_MAX;
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ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_WAIT,
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(void *)&gem_wait), 0) << strerror(errno);
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}
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uint64_t
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__gen_combine_address(gen_mi_builder_test *test, void *location,
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address addr, uint32_t delta)
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{
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drm_i915_gem_relocation_entry reloc = drm_i915_gem_relocation_entry();
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reloc.target_handle = addr.gem_handle == test->data_bo_handle ? 0 : 1;
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reloc.delta = addr.offset + delta;
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reloc.offset = (char *)location - (char *)test->batch_map;
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reloc.presumed_offset = -1;
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test->relocs.push_back(reloc);
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return reloc.delta;
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}
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void *
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__gen_get_batch_dwords(gen_mi_builder_test *test, unsigned num_dwords)
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{
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return test->emit_dwords(num_dwords);
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}
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#include "genxml/genX_pack.h"
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#include "gen_mi_builder.h"
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TEST_F(gen_mi_builder_test, imm_mem)
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{
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const uint64_t value = 0x0123456789abcdef;
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gen_mi_store(&b, out_mem64(0), gen_mi_imm(value));
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gen_mi_store(&b, out_mem32(8), gen_mi_imm(value));
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submit_batch();
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// 64 -> 64
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EXPECT_EQ(*(uint64_t *)(output + 0), value);
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// 64 -> 32
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EXPECT_EQ(*(uint32_t *)(output + 8), (uint32_t)value);
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EXPECT_EQ(*(uint32_t *)(output + 12), (uint32_t)canary);
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}
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TEST_F(gen_mi_builder_test, mem_mem)
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{
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const uint64_t value = 0x0123456789abcdef;
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*(uint64_t *)input = value;
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gen_mi_store(&b, out_mem64(0), in_mem64(0));
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gen_mi_store(&b, out_mem32(8), in_mem64(0));
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gen_mi_store(&b, out_mem32(16), in_mem32(0));
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gen_mi_store(&b, out_mem64(24), in_mem32(0));
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submit_batch();
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// 64 -> 64
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EXPECT_EQ(*(uint64_t *)(output + 0), value);
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// 64 -> 32
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EXPECT_EQ(*(uint32_t *)(output + 8), (uint32_t)value);
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EXPECT_EQ(*(uint32_t *)(output + 12), (uint32_t)canary);
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// 32 -> 32
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EXPECT_EQ(*(uint32_t *)(output + 16), (uint32_t)value);
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EXPECT_EQ(*(uint32_t *)(output + 20), (uint32_t)canary);
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// 32 -> 64
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EXPECT_EQ(*(uint64_t *)(output + 24), (uint64_t)(uint32_t)value);
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}
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TEST_F(gen_mi_builder_test, imm_reg)
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{
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const uint64_t value = 0x0123456789abcdef;
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gen_mi_store(&b, gen_mi_reg64(RSVD_TEMP_REG), gen_mi_imm(canary));
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gen_mi_store(&b, gen_mi_reg64(RSVD_TEMP_REG), gen_mi_imm(value));
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gen_mi_store(&b, out_mem64(0), gen_mi_reg64(RSVD_TEMP_REG));
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gen_mi_store(&b, gen_mi_reg64(RSVD_TEMP_REG), gen_mi_imm(canary));
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gen_mi_store(&b, gen_mi_reg32(RSVD_TEMP_REG), gen_mi_imm(value));
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gen_mi_store(&b, out_mem64(8), gen_mi_reg64(RSVD_TEMP_REG));
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submit_batch();
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// 64 -> 64
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EXPECT_EQ(*(uint64_t *)(output + 0), value);
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// 64 -> 32
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EXPECT_EQ(*(uint32_t *)(output + 8), (uint32_t)value);
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EXPECT_EQ(*(uint32_t *)(output + 12), (uint32_t)canary);
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}
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TEST_F(gen_mi_builder_test, mem_reg)
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{
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const uint64_t value = 0x0123456789abcdef;
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*(uint64_t *)input = value;
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gen_mi_store(&b, gen_mi_reg64(RSVD_TEMP_REG), gen_mi_imm(canary));
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gen_mi_store(&b, gen_mi_reg64(RSVD_TEMP_REG), in_mem64(0));
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gen_mi_store(&b, out_mem64(0), gen_mi_reg64(RSVD_TEMP_REG));
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gen_mi_store(&b, gen_mi_reg64(RSVD_TEMP_REG), gen_mi_imm(canary));
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gen_mi_store(&b, gen_mi_reg32(RSVD_TEMP_REG), in_mem64(0));
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||||
gen_mi_store(&b, out_mem64(8), gen_mi_reg64(RSVD_TEMP_REG));
|
||||
|
||||
gen_mi_store(&b, gen_mi_reg64(RSVD_TEMP_REG), gen_mi_imm(canary));
|
||||
gen_mi_store(&b, gen_mi_reg32(RSVD_TEMP_REG), in_mem32(0));
|
||||
gen_mi_store(&b, out_mem64(16), gen_mi_reg64(RSVD_TEMP_REG));
|
||||
|
||||
gen_mi_store(&b, gen_mi_reg64(RSVD_TEMP_REG), gen_mi_imm(canary));
|
||||
gen_mi_store(&b, gen_mi_reg64(RSVD_TEMP_REG), in_mem32(0));
|
||||
gen_mi_store(&b, out_mem64(24), gen_mi_reg64(RSVD_TEMP_REG));
|
||||
|
||||
submit_batch();
|
||||
|
||||
// 64 -> 64
|
||||
EXPECT_EQ(*(uint64_t *)(output + 0), value);
|
||||
|
||||
// 64 -> 32
|
||||
EXPECT_EQ(*(uint32_t *)(output + 8), (uint32_t)value);
|
||||
EXPECT_EQ(*(uint32_t *)(output + 12), (uint32_t)canary);
|
||||
|
||||
// 32 -> 32
|
||||
EXPECT_EQ(*(uint32_t *)(output + 16), (uint32_t)value);
|
||||
EXPECT_EQ(*(uint32_t *)(output + 20), (uint32_t)canary);
|
||||
|
||||
// 32 -> 64
|
||||
EXPECT_EQ(*(uint64_t *)(output + 24), (uint64_t)(uint32_t)value);
|
||||
}
|
||||
|
||||
/* Start of MI_MATH section */
|
||||
#if GEN_GEN >= 8 || GEN_IS_HASWELL
|
||||
|
||||
/* Test adding of immediates of all kinds including
|
||||
*
|
||||
* - All zeroes
|
||||
* - All ones
|
||||
* - inverted constants
|
||||
*/
|
||||
TEST_F(gen_mi_builder_test, add_imm)
|
||||
{
|
||||
const uint64_t value = 0x0123456789abcdef;
|
||||
const uint64_t add = 0xdeadbeefac0ffee2;
|
||||
memcpy(input, &value, sizeof(value));
|
||||
|
||||
gen_mi_store(&b, out_mem64(0),
|
||||
gen_mi_iadd(&b, in_mem64(0), gen_mi_imm(0)));
|
||||
gen_mi_store(&b, out_mem64(8),
|
||||
gen_mi_iadd(&b, in_mem64(0), gen_mi_imm(-1)));
|
||||
gen_mi_store(&b, out_mem64(16),
|
||||
gen_mi_iadd(&b, in_mem64(0), gen_mi_inot(&b, gen_mi_imm(0))));
|
||||
gen_mi_store(&b, out_mem64(24),
|
||||
gen_mi_iadd(&b, in_mem64(0), gen_mi_inot(&b, gen_mi_imm(-1))));
|
||||
gen_mi_store(&b, out_mem64(32),
|
||||
gen_mi_iadd(&b, in_mem64(0), gen_mi_imm(add)));
|
||||
gen_mi_store(&b, out_mem64(40),
|
||||
gen_mi_iadd(&b, in_mem64(0), gen_mi_inot(&b, gen_mi_imm(add))));
|
||||
gen_mi_store(&b, out_mem64(48),
|
||||
gen_mi_iadd(&b, gen_mi_imm(0), in_mem64(0)));
|
||||
gen_mi_store(&b, out_mem64(56),
|
||||
gen_mi_iadd(&b, gen_mi_imm(-1), in_mem64(0)));
|
||||
gen_mi_store(&b, out_mem64(64),
|
||||
gen_mi_iadd(&b, gen_mi_inot(&b, gen_mi_imm(0)), in_mem64(0)));
|
||||
gen_mi_store(&b, out_mem64(72),
|
||||
gen_mi_iadd(&b, gen_mi_inot(&b, gen_mi_imm(-1)), in_mem64(0)));
|
||||
gen_mi_store(&b, out_mem64(80),
|
||||
gen_mi_iadd(&b, gen_mi_imm(add), in_mem64(0)));
|
||||
gen_mi_store(&b, out_mem64(88),
|
||||
gen_mi_iadd(&b, gen_mi_inot(&b, gen_mi_imm(add)), in_mem64(0)));
|
||||
|
||||
// And som add_imm just for good measure
|
||||
gen_mi_store(&b, out_mem64(96), gen_mi_iadd_imm(&b, in_mem64(0), 0));
|
||||
gen_mi_store(&b, out_mem64(104), gen_mi_iadd_imm(&b, in_mem64(0), add));
|
||||
|
||||
submit_batch();
|
||||
|
||||
EXPECT_EQ(*(uint64_t *)(output + 0), value);
|
||||
EXPECT_EQ(*(uint64_t *)(output + 8), value - 1);
|
||||
EXPECT_EQ(*(uint64_t *)(output + 16), value - 1);
|
||||
EXPECT_EQ(*(uint64_t *)(output + 24), value);
|
||||
EXPECT_EQ(*(uint64_t *)(output + 32), value + add);
|
||||
EXPECT_EQ(*(uint64_t *)(output + 40), value + ~add);
|
||||
EXPECT_EQ(*(uint64_t *)(output + 48), value);
|
||||
EXPECT_EQ(*(uint64_t *)(output + 56), value - 1);
|
||||
EXPECT_EQ(*(uint64_t *)(output + 64), value - 1);
|
||||
EXPECT_EQ(*(uint64_t *)(output + 72), value);
|
||||
EXPECT_EQ(*(uint64_t *)(output + 80), value + add);
|
||||
EXPECT_EQ(*(uint64_t *)(output + 88), value + ~add);
|
||||
EXPECT_EQ(*(uint64_t *)(output + 96), value);
|
||||
EXPECT_EQ(*(uint64_t *)(output + 104), value + add);
|
||||
}
|
||||
|
||||
TEST_F(gen_mi_builder_test, ilt_uge)
|
||||
{
|
||||
uint64_t values[8] = {
|
||||
0x0123456789abcdef,
|
||||
0xdeadbeefac0ffee2,
|
||||
(uint64_t)-1,
|
||||
1,
|
||||
0,
|
||||
1049571,
|
||||
(uint64_t)-240058,
|
||||
20204184,
|
||||
};
|
||||
memcpy(input, values, sizeof(values));
|
||||
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(values); i++) {
|
||||
for (unsigned j = 0; j < ARRAY_SIZE(values); j++) {
|
||||
gen_mi_store(&b, out_mem32(i * 64 + j * 8 + 0),
|
||||
gen_mi_ult(&b, in_mem64(i * 8), in_mem64(j * 8)));
|
||||
gen_mi_store(&b, out_mem32(i * 64 + j * 8 + 4),
|
||||
gen_mi_uge(&b, in_mem64(i * 8), in_mem64(j * 8)));
|
||||
}
|
||||
}
|
||||
|
||||
submit_batch();
|
||||
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(values); i++) {
|
||||
for (unsigned j = 0; j < ARRAY_SIZE(values); j++) {
|
||||
uint32_t *out_u32 = (uint32_t *)(output + i * 64 + j * 8);
|
||||
EXPECT_EQ(out_u32[0], values[i] < values[j] ? ~0u : 0u);
|
||||
EXPECT_EQ(out_u32[1], values[i] >= values[j] ? ~0u : 0u);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TEST_F(gen_mi_builder_test, iand)
|
||||
{
|
||||
const uint64_t values[2] = {
|
||||
0x0123456789abcdef,
|
||||
0xdeadbeefac0ffee2,
|
||||
};
|
||||
memcpy(input, values, sizeof(values));
|
||||
|
||||
gen_mi_store(&b, out_mem64(0), gen_mi_iand(&b, in_mem64(0), in_mem64(8)));
|
||||
|
||||
submit_batch();
|
||||
|
||||
EXPECT_EQ(*(uint64_t *)output, values[0] & values[1]);
|
||||
}
|
||||
|
||||
TEST_F(gen_mi_builder_test, imul_imm)
|
||||
{
|
||||
uint64_t lhs[2] = {
|
||||
0x0123456789abcdef,
|
||||
0xdeadbeefac0ffee2,
|
||||
};
|
||||
memcpy(input, lhs, sizeof(lhs));
|
||||
|
||||
/* Some random 32-bit unsigned integers. The first four have been
|
||||
* hand-chosen just to ensure some good low integers; the rest were
|
||||
* generated with a python script.
|
||||
*/
|
||||
uint32_t rhs[20] = {
|
||||
1, 2, 3, 5,
|
||||
10800, 193, 64, 40,
|
||||
3796, 256, 88, 473,
|
||||
1421, 706, 175, 850,
|
||||
39, 38985, 1941, 17,
|
||||
};
|
||||
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(lhs); i++) {
|
||||
for (unsigned j = 0; j < ARRAY_SIZE(rhs); j++) {
|
||||
gen_mi_store(&b, out_mem64(i * 160 + j * 8),
|
||||
gen_mi_imul_imm(&b, in_mem64(i * 8), rhs[j]));
|
||||
}
|
||||
}
|
||||
|
||||
submit_batch();
|
||||
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(lhs); i++) {
|
||||
for (unsigned j = 0; j < ARRAY_SIZE(rhs); j++) {
|
||||
EXPECT_EQ(*(uint64_t *)(output + i * 160 + j * 8), lhs[i] * rhs[j]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TEST_F(gen_mi_builder_test, ishl_imm)
|
||||
{
|
||||
const uint64_t value = 0x0123456789abcdef;
|
||||
memcpy(input, &value, sizeof(value));
|
||||
|
||||
const unsigned max_shift = 64;
|
||||
|
||||
for (unsigned i = 0; i <= max_shift; i++)
|
||||
gen_mi_store(&b, out_mem64(i * 8), gen_mi_ishl_imm(&b, in_mem64(0), i));
|
||||
|
||||
submit_batch();
|
||||
|
||||
for (unsigned i = 0; i <= max_shift; i++) {
|
||||
if (i >= 64) {
|
||||
EXPECT_EQ(*(uint64_t *)(output + i * 8), 0);
|
||||
} else {
|
||||
EXPECT_EQ(*(uint64_t *)(output + i * 8), value << i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TEST_F(gen_mi_builder_test, ushr32_imm)
|
||||
{
|
||||
const uint64_t value = 0x0123456789abcdef;
|
||||
memcpy(input, &value, sizeof(value));
|
||||
|
||||
const unsigned max_shift = 31;
|
||||
|
||||
for (unsigned i = 0; i <= max_shift; i++)
|
||||
gen_mi_store(&b, out_mem64(i * 8), gen_mi_ushr32_imm(&b, in_mem64(0), i));
|
||||
|
||||
submit_batch();
|
||||
|
||||
for (unsigned i = 0; i <= max_shift; i++)
|
||||
EXPECT_EQ(*(uint64_t *)(output + i * 8), (value >> i) & UINT32_MAX);
|
||||
}
|
||||
|
||||
TEST_F(gen_mi_builder_test, udiv32_imm)
|
||||
{
|
||||
/* Some random 32-bit unsigned integers. The first four have been
|
||||
* hand-chosen just to ensure some good low integers; the rest were
|
||||
* generated with a python script.
|
||||
*/
|
||||
uint32_t values[20] = {
|
||||
1, 2, 3, 5,
|
||||
10800, 193, 64, 40,
|
||||
3796, 256, 88, 473,
|
||||
1421, 706, 175, 850,
|
||||
39, 38985, 1941, 17,
|
||||
};
|
||||
memcpy(input, values, sizeof(values));
|
||||
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(values); i++) {
|
||||
for (unsigned j = 0; j < ARRAY_SIZE(values); j++) {
|
||||
gen_mi_store(&b, out_mem32(i * 80 + j * 4),
|
||||
gen_mi_udiv32_imm(&b, in_mem32(i * 4), values[j]));
|
||||
}
|
||||
}
|
||||
|
||||
submit_batch();
|
||||
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(values); i++) {
|
||||
for (unsigned j = 0; j < ARRAY_SIZE(values); j++) {
|
||||
EXPECT_EQ(*(uint32_t *)(output + i * 80 + j * 4),
|
||||
values[i] / values[j]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
|
||||
Loading…
Reference in New Issue