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radeonsi: DCC MSAA blending bug - include logic op, limit to Navi14 and older 

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
This commit is contained in:
Marek Olšák 2019-07-30 17:28:50 -04:00
parent e69c1c8b8f
commit 8b68511ebc
2 changed files with 9 additions and 2 deletions
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10
src/gallium/drivers/radeonsi/si_state.c
View File

@ -115,12 +115,12 @@ static void si_emit_cb_render_state(struct si_context *sctx)
SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
if (sctx->chip_class >= GFX8) {
/* DCC MSAA workaround for blending.
/* DCC MSAA workaround.
* Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
* COMBINER_DISABLE, but that would be more complicated.
*/
bool oc_disable = blend &&
blend->blend_enable_4bit & cb_target_mask &&
blend->dcc_msaa_corruption_4bit & cb_target_mask &&
sctx->framebuffer.nr_samples >= 2;
unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
@ -621,6 +621,9 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
blend->blend_enable_4bit |= 0xfu << (i * 4);
if (sctx->family <= CHIP_NAVI14)
blend->dcc_msaa_corruption_4bit |= 0xfu << (i * 4);
/* This is only important for formats without alpha. */
if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
@ -631,6 +634,9 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
blend->need_src_alpha_4bit |= 0xfu << (i * 4);
}
if (sctx->family <= CHIP_NAVI14 && logicop_enable)
blend->dcc_msaa_corruption_4bit |= blend->cb_target_enabled_4bit;
if (blend->cb_target_mask) {
color_control |= S_028808_MODE(mode);
} else {

1
src/gallium/drivers/radeonsi/si_state.h
View File

@ -56,6 +56,7 @@ struct si_state_blend {
unsigned blend_enable_4bit;
unsigned need_src_alpha_4bit;
unsigned commutative_4bit;
unsigned dcc_msaa_corruption_4bit;
bool alpha_to_coverage:1;
bool alpha_to_one:1;
bool dual_src_blend:1;