radv: detect command buffers that do no work and drop them (v2)
If a buffer is just full of flushes we flush things on command buffer submission, so don't bother submitting these. This will reduce some CPU overhead on dota2, which submits a fair few command streams that don't end up drawing anything. v2: reorganise loop to count first then malloc, rename some vars (Bas) Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -1277,6 +1277,7 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer)
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MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
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cmd_buffer->cs, 4096);
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cmd_buffer->no_draws = false;
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if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
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cmd_buffer->state.pipeline->num_vertex_attribs) {
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unsigned vb_offset;
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@ -1592,6 +1593,7 @@ static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
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cmd_buffer->record_fail = false;
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cmd_buffer->ring_offsets_idx = -1;
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cmd_buffer->no_draws = true;
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}
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VkResult radv_ResetCommandBuffer(
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@ -2423,6 +2425,7 @@ void radv_CmdDrawIndexedIndirectCountAMD(
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static void
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radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
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{
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cmd_buffer->no_draws = false;
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radv_emit_compute_pipeline(cmd_buffer);
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radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
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VK_SHADER_STAGE_COMPUTE_BIT);
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@ -1452,8 +1452,18 @@ VkResult radv_QueueSubmit(
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struct radeon_winsys_cs **cs_array;
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bool can_patch = true;
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uint32_t advance;
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int draw_cmd_buffers_count = 0;
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if (!pSubmits[i].commandBufferCount) {
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for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
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pSubmits[i].pCommandBuffers[j]);
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assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
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if (cmd_buffer->no_draws == true)
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continue;
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draw_cmd_buffers_count++;
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}
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if (!draw_cmd_buffers_count) {
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if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
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ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
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&queue->device->empty_cs[queue->queue_family_index],
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@ -1472,24 +1482,27 @@ VkResult radv_QueueSubmit(
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continue;
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}
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cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
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pSubmits[i].commandBufferCount);
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cs_array = malloc(sizeof(struct radeon_winsys_cs *) * draw_cmd_buffers_count);
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int draw_cmd_buffer_idx = 0;
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for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
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pSubmits[i].pCommandBuffers[j]);
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assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
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if (cmd_buffer->no_draws == true)
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continue;
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cs_array[j] = cmd_buffer->cs;
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cs_array[draw_cmd_buffer_idx] = cmd_buffer->cs;
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draw_cmd_buffer_idx++;
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if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
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can_patch = false;
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}
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for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
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for (uint32_t j = 0; j < draw_cmd_buffers_count; j += advance) {
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advance = MIN2(max_cs_submission,
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pSubmits[i].commandBufferCount - j);
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draw_cmd_buffers_count - j);
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bool b = j == 0;
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bool e = j + advance == pSubmits[i].commandBufferCount;
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bool e = j + advance == draw_cmd_buffers_count;
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if (queue->device->trace_bo)
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*queue->device->trace_id_ptr = 0;
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@ -523,6 +523,7 @@ void radv_CmdUpdateBuffer(
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assert(!(dataSize & 3));
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assert(!(va & 3));
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cmd_buffer->no_draws = false;
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if (dataSize < 4096) {
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cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, dst_buffer->bo, 8);
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@ -750,6 +750,8 @@ struct radv_cmd_buffer {
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uint32_t gsvs_ring_size_needed;
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int ring_offsets_idx; /* just used for verification */
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bool no_draws;
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};
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struct radv_image;
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@ -828,7 +828,7 @@ static void si_emit_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer,
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static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
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uint64_t remaining_size, unsigned *flags)
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{
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cmd_buffer->no_draws = false;
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/* Flush the caches for the first copy only.
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* Also wait for the previous CP DMA operations.
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*/
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