pan/bi: Remove combine lowering
Unused. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8135>
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/*
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* Copyright (C) 2020 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "compiler.h"
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/* NIR creates vectors as vecN ops, which we represent by a synthetic
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* BI_COMBINE instruction, e.g.:
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*
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* v = combine x, y, z, w
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*
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* These combines need to be lowered by the pass in this file. Fix a given
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* source at component c.
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*
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* First suppose the source is SSA. If it is also scalar, then we may rewrite
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* the destination of the generating instruction (unique by SSA+scalar) to
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* write to v.c, and rewrite each of its uses to swizzle out .c instead of .x
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* (the original by scalar). If it is vector, there are two cases. If the
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* component c is `x`, we are accessing v.x, and each of the succeeding
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* components y, z... up to the last component of the vector are accessed
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* sequentially, then we may perform the same rewrite. If this is not the case,
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* rewriting would require more complex vector features, so we fallback on a
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* move.
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*
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* Otherwise is the source is not SSA, we also fallback on a move. We could
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* probably do better.
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*/
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static void
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bi_combine_mov32(bi_context *ctx, bi_instruction *parent, unsigned comp, unsigned R)
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{
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bi_instruction move = {
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.type = BI_MOV,
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.dest = R,
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.dest_type = nir_type_uint32,
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.dest_offset = comp,
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.src = { parent->src[comp] },
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.src_types = { nir_type_uint32 },
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.swizzle = { { parent->swizzle[comp][0] } }
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};
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bi_emit_before(ctx, parent, move);
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}
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static void
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bi_combine_sel16(bi_context *ctx, bi_instruction *parent, unsigned comp, unsigned R)
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{
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bi_instruction sel = {
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.type = BI_SELECT,
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.dest = R,
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.dest_type = nir_type_uint32,
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.dest_offset = comp >> 1,
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.src = { parent->src[comp], parent->src[comp + 1] },
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.src_types = { nir_type_uint16, nir_type_uint16 },
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.swizzle = {
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{ parent->swizzle[comp][0] },
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{ parent->swizzle[comp + 1][0] },
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}
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};
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/* In case we have a combine from a vec3 */
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if (!sel.src[1])
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sel.src[1] = BIR_INDEX_ZERO;
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bi_emit_before(ctx, parent, sel);
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}
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/* Copies result of combine from the temp R to the instruction destination,
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* given a bitsize sz */
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static void
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bi_combine_copy(bi_context *ctx, bi_instruction *ins, unsigned R, unsigned sz)
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{
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bi_foreach_src(ins, s) {
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if (!ins->src[s])
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continue;
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/* Iterate by 32-bits */
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unsigned shift = (sz == 8) ? 2 :
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(sz == 16) ? 1 : 0;
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if (s & ((1 << shift) - 1))
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continue;
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bi_instruction copy = {
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.type = BI_MOV,
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.dest = ins->dest,
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.dest_type = nir_type_uint32,
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.dest_offset = s >> shift,
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.src = { R },
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.src_types = { nir_type_uint32 },
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.swizzle = { { s >> shift } }
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};
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bi_emit_before(ctx, ins, copy);
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}
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}
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void
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bi_lower_combine(bi_context *ctx, bi_block *block)
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{
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bi_foreach_instr_in_block_safe(block, ins) {
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if (ins->type != BI_COMBINE) continue;
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/* If a register COMBINE reads its own output, we need a
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* temporary move to allow for swapping. TODO: Could do a bit
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* better for pairwise swaps of 16-bit vectors */
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bool reads_self = false;
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bi_foreach_src(ins, s) {
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if(ins->src[s] == ins->dest)
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reads_self = true;
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}
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bool needs_rewrite = !(ins->dest & PAN_IS_REG);
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bool needs_copy = (ins->dest & PAN_IS_REG) && reads_self;
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bool needs_temp = needs_rewrite || needs_copy;
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unsigned R = needs_temp ? bi_make_temp_reg(ctx) : ins->dest;
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unsigned sz = nir_alu_type_get_type_size(ins->dest_type);
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bi_foreach_src(ins, s) {
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/* We're done early for vec2/3 */
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if (!ins->src[s])
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continue;
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if (sz == 32)
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bi_combine_mov32(ctx, ins, s, R);
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else if (sz == 16) {
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bi_combine_sel16(ctx, ins, s, R);
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s++;
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} else {
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unreachable("Unknown COMBINE size");
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}
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}
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if (needs_rewrite)
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bi_rewrite_uses(ctx, ins->dest, 0, R, 0);
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else if (needs_copy)
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bi_combine_copy(ctx, ins, R, sz);
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bi_remove_instruction(ins);
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}
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}
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@ -1085,7 +1085,6 @@ void bi_print_instr(bi_instr *I, FILE *fp);
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/* BIR passes */
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/* BIR passes */
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void bi_lower_combine(bi_context *ctx, bi_block *block);
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bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block);
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bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block);
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void bi_schedule(bi_context *ctx);
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void bi_schedule(bi_context *ctx);
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void bi_register_allocate(bi_context *ctx);
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void bi_register_allocate(bi_context *ctx);
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@ -22,7 +22,6 @@
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libpanfrost_bifrost_files = files(
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libpanfrost_bifrost_files = files(
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'bi_layout.c',
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'bi_layout.c',
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'bi_liveness.c',
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'bi_liveness.c',
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'bi_lower_combine.c',
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'bi_print.c',
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'bi_print.c',
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'bi_opt_dce.c',
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'bi_opt_dce.c',
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'bi_pack.c',
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'bi_pack.c',
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