From 8a69efa171f25524668cea78c19b38d237494e42 Mon Sep 17 00:00:00 2001
From: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Wed, 24 Feb 2021 22:18:37 -0500
Subject: [PATCH] nv50/ir: logic ops on half-regs can't take an immediate

There does not appear to be an instruction form for this. Prevent an
immediate from being loaded into place.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
index 1242afbcf50..1b2f988247a 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
@@ -355,8 +355,11 @@ TargetNV50::insnCanLoad(const Instruction *i, int s,
       ldSize = typeSizeof(ld->dType);
    }
 
-   if (sf == FILE_IMMEDIATE)
+   if (sf == FILE_IMMEDIATE) {
+      if (ldSize == 2 && (i->op == OP_AND || i->op == OP_OR || i->op == OP_XOR))
+         return false;
       return ldSize <= 4;
+   }
 
 
    // Check if memory access is encodable: