radeon/llvm: Use a custom inserter to lower RESERVE_REG

src/gallium/drivers/r600/r600_llvm.c

@@ -93,17 +93,13 @@ static void llvm_emit_prologue(struct lp_build_tgsi_context * bld_base)
 	for (i = 0; i < ctx->reserved_reg_count; i++) {
 		unsigned chan;
 		for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
-			LLVMValueRef reg;
 			LLVMValueRef reg_index = lp_build_const_int32(
 					base->gallivm,
 					radeon_llvm_reg_index_soa(i, chan));
-			reg = lp_build_intrinsic_unary(base->gallivm->builder,
-						"llvm.AMDGPU.reserve.reg",
-						base->elem_type, reg_index);
 			lp_build_intrinsic_unary(base->gallivm->builder,
-				"llvm.AMDGPU.export.reg",
+				"llvm.AMDGPU.reserve.reg",
 				LLVMVoidTypeInContext(base->gallivm->context),
-				reg);
+				reg_index);
 		}
 	}
 }

src/gallium/drivers/radeon/AMDGPUInstructions.td

@@ -48,13 +48,6 @@ let isCodeGenOnly = 1 in {
     "MASK_WRITE $src",
     []
   >;
-
-  def RESERVE_REG : AMDGPUShaderInst <
-    (outs GPRF32:$dst),
-    (ins i32imm:$src),
-    "RESERVE_REG $dst, $src",
-    [(set GPRF32:$dst, (int_AMDGPU_reserve_reg imm:$src))]
-  >;
 }
 
 /* Generic helper patterns for intrinsics */

src/gallium/drivers/radeon/AMDGPUIntrinsics.td

@@ -16,7 +16,7 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
   def int_AMDGPU_export_reg : Intrinsic<[], [llvm_float_ty], []>;
   def int_AMDGPU_load_const : Intrinsic<[llvm_float_ty], [llvm_i32_ty], []>;
   def int_AMDGPU_load_imm : Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], []>;
-  def int_AMDGPU_reserve_reg : Intrinsic<[llvm_float_ty], [llvm_i32_ty], []>;
+  def int_AMDGPU_reserve_reg : Intrinsic<[], [llvm_i32_ty], []>;
   def int_AMDGPU_store_output : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_i32_ty], []>;
   def int_AMDGPU_swizzle : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty], []>;
 

src/gallium/drivers/radeon/Makefile.sources

@@ -51,6 +51,7 @@ CPP_SOURCES := \
 	R600KernelParameters.cpp	\
 	R600LowerInstructions.cpp	\
 	R600LowerShaderInstructions.cpp	\
+	R600MachineFunctionInfo.cpp	\
 	R600RegisterInfo.cpp		\
 	SIAssignInterpRegs.cpp		\
 	SICodeEmitter.cpp		\

src/gallium/drivers/radeon/R600ISelLowering.cpp

@@ -13,6 +13,7 @@
 
 #include "R600ISelLowering.h"
 #include "R600InstrInfo.h"
+#include "R600MachineFunctionInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 
 using namespace llvm;
@@ -112,7 +113,19 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
       MI->eraseFromParent();
       break;
     }
+
+  case AMDIL::RESERVE_REG:
+    {
+      R600MachineFunctionInfo * MFI = MF->getInfo<R600MachineFunctionInfo>();
+      int64_t ReservedIndex = MI->getOperand(0).getImm();
+      unsigned ReservedReg =
+                          AMDIL::R600_TReg32RegClass.getRegister(ReservedIndex);
+      MFI->ReservedRegs.push_back(ReservedReg);
+      MI->eraseFromParent();
+      break;
+    }
   }
+
   return BB;
 }
 

src/gallium/drivers/radeon/R600Instructions.td

@@ -998,6 +998,13 @@ def LOAD_INPUT : AMDGPUShaderInst <
   [(set R600_Reg32:$dst, (int_R600_load_input imm:$src))]
 >;
 
+def RESERVE_REG : AMDGPUShaderInst <
+  (outs),
+  (ins i32imm:$src),
+  "RESERVE_REG $src",
+  [(int_AMDGPU_reserve_reg imm:$src)]
+>;
+
 def STORE_OUTPUT: AMDGPUShaderInst <
   (outs R600_Reg32:$dst),
   (ins R600_Reg32:$src0, i32imm:$src1),

src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp

@@ -72,7 +72,6 @@ bool R600LowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
 
       default: break;
 
-      case AMDIL::RESERVE_REG:
       case AMDIL::EXPORT_REG:
         deleteInstr = true;
         break;

src/gallium/drivers/radeon/R600MachineFunctionInfo.cpp

@@ -0,0 +1,20 @@
+//===-- R600MachineFunctionInfo.cpp - TODO: Add brief description -------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// TODO: Add full description
+//
+//===----------------------------------------------------------------------===//
+
+#include "R600MachineFunctionInfo.h"
+
+using namespace llvm;
+
+R600MachineFunctionInfo::R600MachineFunctionInfo(const MachineFunction &MF)
+  : MachineFunctionInfo()
+  { }

src/gallium/drivers/radeon/R600MachineFunctionInfo.h

@@ -0,0 +1,32 @@
+//===-- R600MachineFunctionInfo.h - TODO: Add brief description ---*- C++ -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// TODO: Add full description
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef R600MACHINEFUNCTIONINFO_H
+#define R600MACHINEFUNCTIONINFO_H
+
+#include "llvm/CodeGen/MachineFunction.h"
+#include <vector>
+
+namespace llvm {
+
+class R600MachineFunctionInfo : public MachineFunctionInfo {
+
+public:
+  R600MachineFunctionInfo(const MachineFunction &MF);
+  std::vector<unsigned> ReservedRegs;
+
+};
+
+} // End llvm namespace
+
+#endif //R600MACHINEFUNCTIONINFO_H

src/gallium/drivers/radeon/R600RegisterInfo.cpp

@@ -13,6 +13,7 @@
 
 #include "R600RegisterInfo.h"
 #include "AMDGPUTargetMachine.h"
+#include "R600MachineFunctionInfo.h"
 
 using namespace llvm;
 
@@ -26,6 +27,8 @@ R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const
 {
   BitVector Reserved(getNumRegs());
+  const R600MachineFunctionInfo * MFI = MF.getInfo<R600MachineFunctionInfo>();
+
   Reserved.set(AMDIL::ZERO);
   Reserved.set(AMDIL::HALF);
   Reserved.set(AMDIL::ONE);
@@ -40,19 +43,11 @@ BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const
     Reserved.set(*I);
   }
 
-  for (MachineFunction::const_iterator BB = MF.begin(),
-                                 BB_E = MF.end(); BB != BB_E; ++BB) {
-    const MachineBasicBlock &MBB = *BB;
-    for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end();
-                                                                  I != E; ++I) {
-      const MachineInstr &MI = *I;
-      if (MI.getOpcode() == AMDIL::RESERVE_REG) {
-        if (!TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg())) {
-          Reserved.set(MI.getOperand(0).getReg());
-        }
-      }
-    }
+  for (std::vector<unsigned>::const_iterator I = MFI->ReservedRegs.begin(),
+                                    E = MFI->ReservedRegs.end(); I != E; ++I) {
+    Reserved.set(*I);
   }
+
   return Reserved;
 }