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anv: fix MI_PREDICATE_RESULT write 

This register is only 32bits.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 1952fd8d2c ("anv: Implement VK_EXT_conditional_rendering for gen 7.5+")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9428>
This commit is contained in:
Lionel Landwerlin 2021-03-05 13:03:07 +02:00 committed by Marge Bot
parent 718bfdb3da
commit 8955d179d3
1 changed files with 1 additions and 1 deletions
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2
src/intel/vulkan/genX_cmd_buffer.c
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@ -4161,7 +4161,7 @@ emit_draw_count_predicate_with_conditional_render(
pred = mi_iand(b, pred, mi_reg64(ANV_PREDICATE_RESULT_REG));
#if GEN_GEN >= 8
mi_store(b, mi_reg64(MI_PREDICATE_RESULT), pred);
mi_store(b, mi_reg32(MI_PREDICATE_RESULT), pred);
#else
/* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
* so we emit MI_PREDICATE to set it.