r600/llvm: Store inputs in function arguments
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23afe71f44
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88c8f19729
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@ -77,6 +77,11 @@ static void llvm_load_system_value(
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default: assert(!"unknown system value");
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}
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#if HAVE_LLVM >= 0x0304
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ctx->system_values[index] = LLVMBuildExtractElement(ctx->gallivm.builder,
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LLVMGetParam(ctx->main_fn, 0), lp_build_const_int32(&(ctx->gallivm), chan),
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"");
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#else
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LLVMValueRef reg = lp_build_const_int32(
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ctx->soa.bld_base.base.gallivm, chan);
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ctx->system_values[index] = build_intrinsic(
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@ -84,8 +89,49 @@ static void llvm_load_system_value(
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"llvm.R600.load.input",
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ctx->soa.bld_base.base.elem_type, ®, 1,
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LLVMReadNoneAttribute);
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#endif
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}
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#if HAVE_LLVM >= 0x0304
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static LLVMValueRef
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llvm_load_input_vector(
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struct radeon_llvm_context * ctx, unsigned location, unsigned ijregs,
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boolean interp)
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{
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LLVMTypeRef VecType;
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LLVMValueRef Args[3] = {
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lp_build_const_int32(&(ctx->gallivm), location)
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};
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unsigned ArgCount = 1;
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if (interp) {
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VecType = LLVMVectorType(ctx->soa.bld_base.base.elem_type, 2);
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LLVMValueRef IJIndex = LLVMGetParam(ctx->main_fn, ijregs / 2);
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Args[ArgCount++] = LLVMBuildExtractElement(ctx->gallivm.builder, IJIndex,
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lp_build_const_int32(&(ctx->gallivm), 2 * (ijregs % 2)), "");
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Args[ArgCount++] = LLVMBuildExtractElement(ctx->gallivm.builder, IJIndex,
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lp_build_const_int32(&(ctx->gallivm), 2 * (ijregs % 2) + 1), "");
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LLVMValueRef HalfVec[2] = {
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build_intrinsic(ctx->gallivm.builder, "llvm.R600.interp.xy",
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VecType, Args, ArgCount, LLVMReadNoneAttribute),
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build_intrinsic(ctx->gallivm.builder, "llvm.R600.interp.zw",
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VecType, Args, ArgCount, LLVMReadNoneAttribute)
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};
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LLVMValueRef MaskInputs[4] = {
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lp_build_const_int32(&(ctx->gallivm), 0),
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lp_build_const_int32(&(ctx->gallivm), 1),
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lp_build_const_int32(&(ctx->gallivm), 2),
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lp_build_const_int32(&(ctx->gallivm), 3)
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};
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LLVMValueRef Mask = LLVMConstVector(MaskInputs, 4);
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return LLVMBuildShuffleVector(ctx->gallivm.builder, HalfVec[0], HalfVec[1],
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Mask, "");
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} else {
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VecType = LLVMVectorType(ctx->soa.bld_base.base.elem_type, 4);
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return build_intrinsic(ctx->gallivm.builder, "llvm.R600.interp.const",
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VecType, Args, ArgCount, LLVMReadNoneAttribute);
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}
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}
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#else
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static LLVMValueRef
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llvm_load_input_helper(
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struct radeon_llvm_context * ctx,
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@ -110,7 +156,22 @@ llvm_load_input_helper(
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return build_intrinsic(bb->gallivm->builder, intrinsic,
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bb->elem_type, &arg[0], arg_count, LLVMReadNoneAttribute);
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}
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#endif
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#if HAVE_LLVM >= 0x0304
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static LLVMValueRef
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llvm_face_select_helper(
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struct radeon_llvm_context * ctx,
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LLVMValueRef face, LLVMValueRef front_color, LLVMValueRef back_color)
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{
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const struct lp_build_context * bb = &ctx->soa.bld_base.base;
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LLVMValueRef is_front = LLVMBuildFCmp(
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bb->gallivm->builder, LLVMRealUGT, face,
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lp_build_const_float(bb->gallivm, 0.0f), "");
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return LLVMBuildSelect(bb->gallivm->builder, is_front,
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front_color, back_color, "");
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}
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#else
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static LLVMValueRef
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llvm_face_select_helper(
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struct radeon_llvm_context * ctx,
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@ -124,6 +185,7 @@ llvm_face_select_helper(
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return LLVMBuildSelect(bb->gallivm->builder, is_front,
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front_color, back_color, "");
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}
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#endif
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static void llvm_load_input(
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struct radeon_llvm_context * ctx,
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@ -132,11 +194,55 @@ static void llvm_load_input(
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{
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const struct r600_shader_io * input = &ctx->r600_inputs[input_index];
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unsigned chan;
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#if HAVE_LLVM < 0x0304
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unsigned interp = 0;
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int ij_index;
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#endif
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int two_side = (ctx->two_side && input->name == TGSI_SEMANTIC_COLOR);
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LLVMValueRef v;
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#if HAVE_LLVM >= 0x0304
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boolean require_interp_intrinsic = ctx->chip_class >= EVERGREEN &&
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ctx->type == TGSI_PROCESSOR_FRAGMENT;
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#endif
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#if HAVE_LLVM >= 0x0304
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if (require_interp_intrinsic && input->spi_sid) {
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v = llvm_load_input_vector(ctx, input->lds_pos, input->ij_index,
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(input->interpolate > 0));
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} else
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v = LLVMGetParam(ctx->main_fn, input->gpr);
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if (two_side) {
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struct r600_shader_io * back_input =
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&ctx->r600_inputs[input->back_color_input];
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LLVMValueRef v2;
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LLVMValueRef face = LLVMGetParam(ctx->main_fn, ctx->face_gpr);
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face = LLVMBuildExtractElement(ctx->gallivm.builder, face,
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lp_build_const_int32(&(ctx->gallivm), 0), "");
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if (require_interp_intrinsic && back_input->spi_sid)
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v2 = llvm_load_input_vector(ctx, back_input->lds_pos,
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back_input->ij_index, (back_input->interpolate > 0));
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else
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v2 = LLVMGetParam(ctx->main_fn, back_input->gpr);
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v = llvm_face_select_helper(ctx, face, v, v2);
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}
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for (chan = 0; chan < 4; chan++) {
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unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
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ctx->inputs[soa_index] = LLVMBuildExtractElement(ctx->gallivm.builder, v,
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lp_build_const_int32(&(ctx->gallivm), chan), "");
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if (input->name == TGSI_SEMANTIC_POSITION &&
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ctx->type == TGSI_PROCESSOR_FRAGMENT && chan == 3) {
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/* RCP for fragcoord.w */
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ctx->inputs[soa_index] = LLVMBuildFDiv(ctx->gallivm.builder,
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lp_build_const_float(&(ctx->gallivm), 1.0f),
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ctx->inputs[soa_index], "");
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}
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}
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#else
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if (ctx->chip_class >= EVERGREEN && ctx->type == TGSI_PROCESSOR_FRAGMENT &&
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input->spi_sid) {
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interp = 1;
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@ -177,6 +283,7 @@ static void llvm_load_input(
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ctx->inputs[soa_index] = v;
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}
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#endif
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}
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static void llvm_emit_prologue(struct lp_build_tgsi_context * bld_base)
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@ -657,7 +764,19 @@ LLVMModuleRef r600_tgsi_llvm(
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struct tgsi_shader_info shader_info;
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struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
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radeon_llvm_context_init(ctx);
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#if HAVE_LLVM >= 0x0304
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LLVMTypeRef Arguments[32];
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unsigned ArgumentsCount = 0;
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for (unsigned i = 0; i < ctx->inputs_count; i++)
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Arguments[ArgumentsCount++] = LLVMVectorType(bld_base->base.elem_type, 4);
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radeon_llvm_create_func(ctx, Arguments, ArgumentsCount);
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for (unsigned i = 0; i < ctx->inputs_count; i++) {
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LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
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LLVMAddAttribute(P, LLVMInRegAttribute);
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}
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#else
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radeon_llvm_create_func(ctx, NULL, 0);
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#endif
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tgsi_scan_shader(tokens, &shader_info);
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bld_base->info = &shader_info;
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@ -1102,6 +1102,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
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radeon_llvm_ctx.type = ctx.type;
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radeon_llvm_ctx.two_side = shader->two_side;
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radeon_llvm_ctx.face_gpr = ctx.face_gpr;
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radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
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radeon_llvm_ctx.r600_inputs = ctx.shader->input;
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radeon_llvm_ctx.r600_outputs = ctx.shader->output;
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radeon_llvm_ctx.color_buffer_count = max_color_exports;
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@ -60,6 +60,7 @@ struct radeon_llvm_context {
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unsigned face_gpr;
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unsigned two_side;
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unsigned clip_vertex;
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unsigned inputs_count;
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struct r600_shader_io * r600_inputs;
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struct r600_shader_io * r600_outputs;
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struct pipe_stream_output_info *stream_outputs;
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