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spirv,vulkan: Set shader_info::subgroup_size 

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17337>
This commit is contained in:
Jason Ekstrand 2022-07-07 13:29:08 -05:00 committed by Marge Bot
parent beb5b17d82
commit 8851f50753
6 changed files with 61 additions and 4 deletions
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22
src/compiler/shader_enums.h
View File

@ -1223,13 +1223,29 @@ enum PACKED gl_subgroup_size
/** Actual subgroup size, whatever that happens to be */
SUBGROUP_SIZE_VARYING = 0,
/** Subgroup size must appear to be the API advertised constant
*
* This is the default Vulkan 1.1 behavior
*/
SUBGROUP_SIZE_API_CONSTANT,
/** Subgroup size must actually be the API advertised constant
*
* Not only must the subgroup size match the API advertised constant as
* with SUBGROUP_SIZE_API_CONSTANT but it must also be dispatched such that
* all the subgroups are full if there are enough invocations.
*/
SUBGROUP_SIZE_FULL_SUBGROUPS,
/* These enums are specifically chosen so that the value of the enum is
* also the subgroup size. If any new values are added, they must respect
* this invariant.
*/
SUBGROUP_SIZE_REQUIRE_8 = 8, /**< VK_EXT_subgroup_size_control */
SUBGROUP_SIZE_REQUIRE_16 = 16, /**< VK_EXT_subgroup_size_control */
SUBGROUP_SIZE_REQUIRE_32 = 32, /**< VK_EXT_subgroup_size_control */
SUBGROUP_SIZE_REQUIRE_8 = 8, /**< VK_EXT_subgroup_size_control */
SUBGROUP_SIZE_REQUIRE_16 = 16, /**< VK_EXT_subgroup_size_control */
SUBGROUP_SIZE_REQUIRE_32 = 32, /**< VK_EXT_subgroup_size_control */
SUBGROUP_SIZE_REQUIRE_64 = 64, /**< VK_EXT_subgroup_size_control */
SUBGROUP_SIZE_REQUIRE_128 = 128, /**< VK_EXT_subgroup_size_control */
};
#ifdef __cplusplus

3
src/compiler/spirv/nir_spirv.h
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@ -75,6 +75,9 @@ struct spirv_to_nir_options {
*/
uint16_t float_controls_execution_mode;
/* Initial subgroup size. This may be overwritten for CL kernels */
enum gl_subgroup_size subgroup_size;
/* True if RelaxedPrecision-decorated ALU result values should be performed
* with 16-bit math.
*/

2
src/compiler/spirv/spirv_to_nir.c
View File

@ -5262,6 +5262,7 @@ vtn_handle_execution_mode(struct vtn_builder *b, struct vtn_value *entry_point,
case SpvExecutionModeSubgroupSize:
vtn_assert(b->shader->info.stage == MESA_SHADER_KERNEL);
vtn_assert(b->shader->info.subgroup_size == SUBGROUP_SIZE_VARYING);
b->shader->info.subgroup_size = mode->operands[0];
break;
@ -6482,6 +6483,7 @@ spirv_to_nir(const uint32_t *words, size_t word_count,
words+= 5;
b->shader = nir_shader_create(b, stage, nir_options, NULL);
b->shader->info.subgroup_size = options->subgroup_size;
b->shader->info.float_controls_execution_mode = options->float_controls_execution_mode;
/* Handle all the preamble instructions */

2
src/vulkan/runtime/vk_nir.c
View File

@ -68,6 +68,7 @@ nir_shader *
vk_spirv_to_nir(struct vk_device *device,
const uint32_t *spirv_data, size_t spirv_size_B,
gl_shader_stage stage, const char *entrypoint_name,
enum gl_subgroup_size subgroup_size,
const VkSpecializationInfo *spec_info,
const struct spirv_to_nir_options *spirv_options,
const struct nir_shader_compiler_options *nir_options,
@ -79,6 +80,7 @@ vk_spirv_to_nir(struct vk_device *device,
struct spirv_to_nir_options spirv_options_local = *spirv_options;
spirv_options_local.debug.func = spirv_nir_debug;
spirv_options_local.debug.private_data = (void *)device;
spirv_options_local.subgroup_size = subgroup_size;
uint32_t num_spec_entries = 0;
struct nir_spirv_specialization *spec_entries =

1
src/vulkan/runtime/vk_nir.h
View File

@ -40,6 +40,7 @@ nir_shader *
vk_spirv_to_nir(struct vk_device *device,
const uint32_t *spirv_data, size_t spirv_size_B,
gl_shader_stage stage, const char *entrypoint_name,
enum gl_subgroup_size subgroup_size,
const VkSpecializationInfo *spec_info,
const struct spirv_to_nir_options *spirv_options,
const struct nir_shader_compiler_options *nir_options,

35
src/vulkan/runtime/vk_pipeline.c
View File

@ -32,6 +32,15 @@
#include "util/mesa-sha1.h"
static uint32_t
get_required_subgroup_size(const VkPipelineShaderStageCreateInfo *info)
{
const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *rss_info =
vk_find_struct_const(info->pNext,
PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
return rss_info != NULL ? rss_info->requiredSubgroupSize : 0;
}
VkResult
vk_pipeline_shader_stage_to_nir(struct vk_device *device,
const VkPipelineShaderStageCreateInfo *info,
@ -80,8 +89,26 @@ vk_pipeline_shader_stage_to_nir(struct vk_device *device,
spirv_size = minfo->codeSize;
}
enum gl_subgroup_size subgroup_size;
uint32_t req_subgroup_size = get_required_subgroup_size(info);
if (req_subgroup_size > 0) {
assert(util_is_power_of_two_nonzero(req_subgroup_size));
assert(req_subgroup_size >= 8 && req_subgroup_size <= 128);
subgroup_size = req_subgroup_size;
} else if (info->flags & VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT ||
vk_spirv_version(spirv_data, spirv_size) >= 0x10600) {
/* Starting with SPIR-V 1.6, varying subgroup size the default */
subgroup_size = SUBGROUP_SIZE_VARYING;
} else if (info->flags & VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT_EXT) {
assert(stage == MESA_SHADER_COMPUTE);
subgroup_size = SUBGROUP_SIZE_FULL_SUBGROUPS;
} else {
subgroup_size = SUBGROUP_SIZE_API_CONSTANT;
}
nir_shader *nir = vk_spirv_to_nir(device, spirv_data, spirv_size, stage,
info->pName, info->pSpecializationInfo,
info->pName, subgroup_size,
info->pSpecializationInfo,
spirv_options, nir_options, mem_ctx);
if (nir == NULL)
return vk_errorf(device, VK_ERROR_UNKNOWN, "spirv_to_nir failed");
@ -126,6 +153,8 @@ vk_pipeline_hash_shader_stage(const VkPipelineShaderStageCreateInfo *info,
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, &info->flags, sizeof(info->flags));
assert(util_bitcount(info->stage) == 1);
_mesa_sha1_update(&ctx, &info->stage, sizeof(info->stage));
@ -153,5 +182,9 @@ vk_pipeline_hash_shader_stage(const VkPipelineShaderStageCreateInfo *info,
_mesa_sha1_update(&ctx, info->pSpecializationInfo->pData,
info->pSpecializationInfo->dataSize);
}
uint32_t req_subgroup_size = get_required_subgroup_size(info);
_mesa_sha1_update(&ctx, &req_subgroup_size, sizeof(req_subgroup_size));
_mesa_sha1_final(&ctx, stage_sha1);
}