radeonsi/gfx9: emit FLUSH_DFSM where required
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -259,6 +259,7 @@ struct si_context {
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struct r600_atom msaa_config;
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struct r600_atom msaa_config;
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struct si_sample_mask sample_mask;
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struct si_sample_mask sample_mask;
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struct r600_atom cb_render_state;
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struct r600_atom cb_render_state;
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unsigned last_cb_target_mask;
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struct si_blend_color blend_color;
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struct si_blend_color blend_color;
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struct r600_atom clip_regs;
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struct r600_atom clip_regs;
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struct si_clip_state clip_state;
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struct si_clip_state clip_state;
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@ -117,6 +117,17 @@ static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *a
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radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
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radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
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/* GFX9: Flush DFSM when CB_TARGET_MASK changes.
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* I think we don't have to do anything between IBs.
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*/
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if (sctx->b.chip_class >= GFX9 &&
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sctx->last_cb_target_mask != cb_target_mask) {
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sctx->last_cb_target_mask = cb_target_mask;
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
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}
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/* RB+ register settings. */
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/* RB+ register settings. */
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if (sctx->screen->b.rbplus_allowed) {
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if (sctx->screen->b.rbplus_allowed) {
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unsigned spi_shader_col_format =
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unsigned spi_shader_col_format =
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@ -2877,6 +2888,12 @@ static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
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sctx->ps_iter_samples,
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sctx->ps_iter_samples,
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sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
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sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
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sc_mode_cntl_1);
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sc_mode_cntl_1);
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/* GFX9: Flush DFSM when the AA mode changes. */
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if (sctx->b.chip_class >= GFX9) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
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}
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}
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}
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static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
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static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
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