radeonsi: remove si_vid_join_surfaces and use combined planar allocations
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
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0f7c9dad44
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86e60bc265
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@ -455,3 +455,43 @@ vl_video_buffer_create_ex2(struct pipe_context *pipe,
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return &buffer->base;
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}
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/* Create pipe_video_buffer by using resource_create with planar formats. */
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struct pipe_video_buffer *
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vl_video_buffer_create_as_resource(struct pipe_context *pipe,
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const struct pipe_video_buffer *tmpl)
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{
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struct pipe_resource templ, *resources[VL_NUM_COMPONENTS] = {};
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unsigned array_size = tmpl->interlaced ? 2 : 1;
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memset(&templ, 0, sizeof(templ));
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templ.target = array_size > 1 ? PIPE_TEXTURE_2D_ARRAY : PIPE_TEXTURE_2D;
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templ.width0 = align(tmpl->width, VL_MACROBLOCK_WIDTH);
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templ.height0 = align(tmpl->height / array_size, VL_MACROBLOCK_HEIGHT);
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templ.depth0 = 1;
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templ.array_size = array_size;
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templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET | tmpl->bind;
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templ.usage = PIPE_USAGE_DEFAULT;
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if (tmpl->buffer_format == PIPE_FORMAT_YUYV)
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templ.format = PIPE_FORMAT_R8G8_R8B8_UNORM;
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else if (tmpl->buffer_format == PIPE_FORMAT_UYVY)
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templ.format = PIPE_FORMAT_G8R8_B8R8_UNORM;
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else
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templ.format = tmpl->buffer_format;
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resources[0] = pipe->screen->resource_create(pipe->screen, &templ);
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if (!resources[0])
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return NULL;
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if (resources[0]->next) {
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pipe_resource_reference(&resources[1], resources[0]->next);
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if (resources[1]->next)
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pipe_resource_reference(&resources[2], resources[1]->next);
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}
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struct pipe_video_buffer vidtemplate = *tmpl;
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vidtemplate.width = templ.width0;
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vidtemplate.height = templ.height0 * array_size;
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return vl_video_buffer_create_ex2(pipe, &vidtemplate, resources);
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}
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@ -145,4 +145,9 @@ vl_video_buffer_create_ex2(struct pipe_context *pipe,
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const struct pipe_video_buffer *templat,
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struct pipe_resource *resources[VL_NUM_COMPONENTS]);
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/* Create pipe_video_buffer by using resource_create with planar formats. */
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struct pipe_video_buffer *
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vl_video_buffer_create_as_resource(struct pipe_context *pipe,
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const struct pipe_video_buffer *tmpl);
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#endif /* vl_video_buffer_h */
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@ -125,89 +125,3 @@ void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffe
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si_sdma_clear_buffer(sctx, &buffer->res->b.b, 0, buffer->res->b.b.width0, 0);
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context->flush(context, NULL, 0);
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}
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/**
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* join surfaces into the same buffer with identical tiling params
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* sumup their sizes and replace the backend buffers with a single bo
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*/
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void si_vid_join_surfaces(struct si_context *sctx,
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struct pb_buffer** buffers[VL_NUM_COMPONENTS],
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struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
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{
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struct radeon_winsys *ws = sctx->ws;;
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unsigned best_tiling, best_wh, off;
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unsigned size, alignment;
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struct pb_buffer *pb;
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unsigned i, j;
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for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
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unsigned wh;
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if (!surfaces[i])
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continue;
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if (sctx->chip_class < GFX9) {
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/* choose the smallest bank w/h for now */
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wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
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if (wh < best_wh) {
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best_wh = wh;
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best_tiling = i;
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}
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}
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}
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for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (!surfaces[i])
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continue;
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/* adjust the texture layer offsets */
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off = align(off, surfaces[i]->surf_alignment);
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if (sctx->chip_class < GFX9) {
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/* copy the tiling parameters */
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surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
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surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;
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surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
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surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
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for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j)
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surfaces[i]->u.legacy.level[j].offset += off;
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} else {
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surfaces[i]->u.gfx9.surf_offset += off;
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for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.gfx9.offset); ++j)
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surfaces[i]->u.gfx9.offset[j] += off;
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}
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surfaces[i]->flags |= RADEON_SURF_IMPORTED;
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off += surfaces[i]->surf_size;
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}
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for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (!buffers[i] || !*buffers[i])
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continue;
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size = align(size, (*buffers[i])->alignment);
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size += (*buffers[i])->size;
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alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
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}
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if (!size)
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return;
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/* TODO: 2D tiling workaround */
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alignment *= 2;
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pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM,
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RADEON_FLAG_GTT_WC);
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if (!pb)
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return;
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for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (!buffers[i] || !*buffers[i])
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continue;
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pb_reference(buffers[i], pb);
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}
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pb_reference(&pb, NULL);
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}
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@ -60,10 +60,4 @@ bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_cmdbuf *cs,
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/* clear the buffer with zeros */
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void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer);
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/* join surfaces into the same buffer with identical tiling params
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sumup their sizes and replace the backend buffers with a single bo */
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void si_vid_join_surfaces(struct si_context *sctx,
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struct pb_buffer** buffers[VL_NUM_COMPONENTS],
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struct radeon_surf *surfaces[VL_NUM_COMPONENTS]);
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#endif // RADEON_VIDEO_H
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@ -129,7 +129,7 @@ driver_radeonsi = declare_dependency(
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compile_args : '-DGALLIUM_RADEONSI',
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sources : si_driinfo_h,
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link_with : [
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libradeonsi, libradeonwinsys, libamdgpuwinsys, libamd_common, libamd_common_llvm
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libradeonsi, libradeonwinsys, libamdgpuwinsys, libamd_common, libamd_common_llvm, libgalliumvl
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],
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dependencies : idep_nir,
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)
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@ -40,71 +40,11 @@
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struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
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const struct pipe_video_buffer *tmpl)
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{
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struct si_context *ctx = (struct si_context *)pipe;
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struct si_texture *resources[VL_NUM_COMPONENTS] = {};
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struct radeon_surf *surfaces[VL_NUM_COMPONENTS] = {};
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struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
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enum pipe_format resource_formats[VL_NUM_COMPONENTS];
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struct pipe_video_buffer vidtemplate;
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struct pipe_resource templ;
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unsigned i, array_size;
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assert(pipe);
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/* first create the needed resources as "normal" textures */
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vl_get_video_buffer_formats(pipe->screen, tmpl->buffer_format, resource_formats);
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array_size = tmpl->interlaced ? 2 : 1;
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vidtemplate = *tmpl;
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vidtemplate.width = align(tmpl->width, VL_MACROBLOCK_WIDTH);
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vidtemplate.height = align(tmpl->height / array_size, VL_MACROBLOCK_HEIGHT);
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assert(resource_formats[0] != PIPE_FORMAT_NONE);
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for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (resource_formats[i] != PIPE_FORMAT_NONE) {
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vl_video_buffer_template(&templ, &vidtemplate,
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resource_formats[i], 1,
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array_size, PIPE_USAGE_DEFAULT, i);
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/* Set PIPE_BIND_SHARED to avoid reallocation in si_texture_get_handle,
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* which can't handle joined surfaces. */
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struct pipe_video_buffer vidbuf = *tmpl;
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/* TODO: get tiling working */
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templ.bind = PIPE_BIND_LINEAR | PIPE_BIND_SHARED;
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resources[i] = (struct si_texture *)
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pipe->screen->resource_create(pipe->screen, &templ);
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if (!resources[i])
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goto error;
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}
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}
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vidbuf.bind |= PIPE_BIND_LINEAR;
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for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (!resources[i])
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continue;
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surfaces[i] = & resources[i]->surface;
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pbs[i] = &resources[i]->buffer.buf;
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}
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si_vid_join_surfaces(ctx, pbs, surfaces);
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for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (!resources[i])
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continue;
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/* reset the address */
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resources[i]->buffer.gpu_address = ctx->ws->buffer_get_virtual_address(
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resources[i]->buffer.buf);
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resources[i]->buffer.bo_size = resources[i]->buffer.buf->size;
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}
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vidtemplate.height *= array_size;
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return vl_video_buffer_create_ex2(pipe, &vidtemplate, (struct pipe_resource **)resources);
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error:
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for (i = 0; i < VL_NUM_COMPONENTS; ++i)
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si_texture_reference(&resources[i], NULL);
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return NULL;
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return vl_video_buffer_create_as_resource(pipe, &vidbuf);
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}
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/* set the decoding target buffer offsets */
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