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i965: Disable write masking when setting up texturing m0. 

v2/Kayden: Also disable write masking in the vec4 backend.

Fixes 78 oglconform glsl-bif-tex-* subcases.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com> [v1]
Reviewed-by: Eric Anholt <eric@anholt.net> [v2]
This commit is contained in:
Eric Anholt 2012-08-30 11:07:52 -07:00 committed by Kenneth Graunke
parent e062a4187d
commit 86536a321d
2 changed files with 4 additions and 1 deletions
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1
src/mesa/drivers/dri/i965/brw_fs_emit.cpp
View File

@ -469,6 +469,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
*/
if (inst->texture_offset) {
brw_push_insn_state(p);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
/* Explicitly set up the message header by copying g0 to the MRF. */
brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),

4
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
View File

@ -335,6 +335,8 @@ vec4_generator::generate_tex(vec4_instruction *inst,
*/
if (inst->texture_offset) {
/* Explicitly set up the message header by copying g0 to the MRF. */
brw_push_insn_state(p);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
@ -344,7 +346,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
BRW_REGISTER_TYPE_UD),
brw_imm_uw(inst->texture_offset));
brw_set_access_mode(p, BRW_ALIGN_16);
brw_pop_insn_state(p);
} else if (inst->header_present) {
/* Set up an implied move from g0 to the MRF. */
src = brw_vec8_grf(0, 0);