radv: check if DCC is enabled per mip not for the whole image
In other words, make use of radv_dcc_enabled() instead of radv_image_has_dcc() all over the places. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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79a30543ee
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864ddda8a3
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@ -1294,7 +1294,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
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}
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}
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}
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}
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if (radv_image_has_dcc(image)) {
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if (radv_dcc_enabled(image, iview->base_mip)) {
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/* Drawing with DCC enabled also compresses colorbuffers. */
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/* Drawing with DCC enabled also compresses colorbuffers. */
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VkImageSubresourceRange range = {
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VkImageSubresourceRange range = {
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.aspectMask = iview->aspect_mask,
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.aspectMask = iview->aspect_mask,
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@ -1624,7 +1624,7 @@ radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
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uint32_t level_count = radv_get_levelCount(image, range);
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uint32_t level_count = radv_get_levelCount(image, range);
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uint32_t count = 2 * level_count;
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uint32_t count = 2 * level_count;
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assert(radv_image_has_dcc(image));
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assert(radv_dcc_enabled(image, range->baseMipLevel));
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
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radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
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radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
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@ -1652,7 +1652,7 @@ radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
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uint32_t level_count = radv_get_levelCount(image, range);
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uint32_t level_count = radv_get_levelCount(image, range);
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uint32_t count = 2 * level_count;
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uint32_t count = 2 * level_count;
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assert(radv_image_has_dcc(image));
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assert(radv_dcc_enabled(image, range->baseMipLevel));
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
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radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
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radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
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@ -1714,7 +1714,8 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
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uint32_t level_count = radv_get_levelCount(image, range);
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uint32_t level_count = radv_get_levelCount(image, range);
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uint32_t count = 2 * level_count;
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uint32_t count = 2 * level_count;
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assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
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assert(radv_image_has_cmask(image) ||
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radv_dcc_enabled(image, range->baseMipLevel));
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radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
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radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
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radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
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radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
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@ -1747,7 +1748,8 @@ radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
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.layerCount = iview->layer_count,
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.layerCount = iview->layer_count,
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};
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};
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assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
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assert(radv_image_has_cmask(image) ||
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radv_dcc_enabled(image, iview->base_mip));
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radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
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radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
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@ -1767,7 +1769,8 @@ radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
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struct radv_image *image = iview->image;
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struct radv_image *image = iview->image;
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uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
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uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
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if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
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if (!radv_image_has_cmask(image) &&
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!radv_dcc_enabled(image, iview->base_mip))
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return;
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return;
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uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
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uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
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@ -4945,7 +4948,7 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
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radv_initialize_fmask(cmd_buffer, image);
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radv_initialize_fmask(cmd_buffer, image);
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}
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}
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if (radv_image_has_dcc(image)) {
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if (radv_dcc_enabled(image, range->baseMipLevel)) {
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uint32_t value = 0xffffffffu; /* Fully expanded mode. */
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uint32_t value = 0xffffffffu; /* Fully expanded mode. */
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bool need_decompress_pass = false;
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bool need_decompress_pass = false;
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@ -4961,7 +4964,8 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
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need_decompress_pass);
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need_decompress_pass);
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}
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}
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if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
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if (radv_image_has_cmask(image) ||
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radv_dcc_enabled(image, range->baseMipLevel)) {
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uint32_t color_values[2] = {};
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uint32_t color_values[2] = {};
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radv_set_color_clear_metadata(cmd_buffer, image, range,
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radv_set_color_clear_metadata(cmd_buffer, image, range,
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color_values);
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color_values);
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@ -4987,7 +4991,7 @@ static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffe
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return;
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return;
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}
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}
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if (radv_image_has_dcc(image)) {
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if (radv_dcc_enabled(image, range->baseMipLevel)) {
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if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
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if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
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radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
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radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
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} else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
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} else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
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@ -4202,7 +4202,7 @@ radv_init_dcc_control_reg(struct radv_device *device,
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unsigned max_compressed_block_size;
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unsigned max_compressed_block_size;
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unsigned independent_64b_blocks;
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unsigned independent_64b_blocks;
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if (!radv_image_has_dcc(iview->image))
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if (!radv_dcc_enabled(iview->image, iview->base_mip))
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return 0;
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return 0;
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if (iview->image->info.samples > 1) {
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if (iview->image->info.samples > 1) {
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@ -1469,7 +1469,7 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
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clear_color, &clear_value))
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clear_color, &clear_value))
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return false;
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return false;
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if (radv_image_has_dcc(iview->image)) {
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if (radv_dcc_enabled(iview->image, iview->base_mip)) {
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bool can_avoid_fast_clear_elim;
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bool can_avoid_fast_clear_elim;
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uint32_t reset_value;
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uint32_t reset_value;
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@ -1518,7 +1518,7 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
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cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
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cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
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/* clear cmask buffer */
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/* clear cmask buffer */
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if (radv_image_has_dcc(iview->image)) {
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if (radv_dcc_enabled(iview->image, iview->base_mip)) {
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uint32_t reset_value;
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uint32_t reset_value;
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bool can_avoid_fast_clear_elim;
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bool can_avoid_fast_clear_elim;
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bool need_decompress_pass = false;
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bool need_decompress_pass = false;
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@ -87,7 +87,7 @@ blit_surf_for_image_level_layer(struct radv_image *image,
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{
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{
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VkFormat format = radv_get_aspect_format(image, aspect_mask);
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VkFormat format = radv_get_aspect_format(image, aspect_mask);
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if (!radv_image_has_dcc(image) &&
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if (!radv_dcc_enabled(image, subres->mipLevel) &&
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!(radv_image_is_tc_compat_htile(image)))
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!(radv_image_is_tc_compat_htile(image)))
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format = vk_format_for_size(vk_format_get_blocksize(format));
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format = vk_format_for_size(vk_format_get_blocksize(format));
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@ -704,7 +704,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
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assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
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assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
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if (decompress_dcc && radv_image_has_dcc(image)) {
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if (decompress_dcc && radv_dcc_enabled(image, subresourceRange->baseMipLevel)) {
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pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.dcc_decompress_pipeline;
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pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.dcc_decompress_pipeline;
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} else if (radv_image_has_fmask(image)) {
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} else if (radv_image_has_fmask(image)) {
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pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.fmask_decompress_pipeline;
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pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.fmask_decompress_pipeline;
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@ -712,7 +712,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
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pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline;
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pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline;
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}
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}
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if (radv_image_has_dcc(image)) {
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if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) {
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uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset :
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uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset :
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image->fce_pred_offset;
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image->fce_pred_offset;
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pred_offset += 8 * subresourceRange->baseMipLevel;
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pred_offset += 8 * subresourceRange->baseMipLevel;
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@ -725,7 +725,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
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radv_process_color_image(cmd_buffer, image, subresourceRange, pipeline);
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radv_process_color_image(cmd_buffer, image, subresourceRange, pipeline);
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if (radv_image_has_dcc(image)) {
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if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) {
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uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset :
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uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset :
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image->fce_pred_offset;
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image->fce_pred_offset;
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pred_offset += 8 * subresourceRange->baseMipLevel;
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pred_offset += 8 * subresourceRange->baseMipLevel;
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@ -742,7 +742,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
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}
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}
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}
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}
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if (radv_image_has_dcc(image)) {
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if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) {
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/* Clear the image's fast-clear eliminate predicate because
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/* Clear the image's fast-clear eliminate predicate because
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* FMASK and DCC also imply a fast-clear eliminate.
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* FMASK and DCC also imply a fast-clear eliminate.
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*/
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*/
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@ -506,7 +506,7 @@ void radv_CmdResolveImage(
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const struct VkOffset3D dstOffset =
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const struct VkOffset3D dstOffset =
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radv_sanitize_image_offset(dest_image->type, region->dstOffset);
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radv_sanitize_image_offset(dest_image->type, region->dstOffset);
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if (radv_image_has_dcc(dest_image)) {
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if (radv_dcc_enabled(dest_image, region->dstSubresource.mipLevel)) {
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VkImageSubresourceRange range = {
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VkImageSubresourceRange range = {
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.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
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.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
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.baseMipLevel = region->dstSubresource.mipLevel,
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.baseMipLevel = region->dstSubresource.mipLevel,
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@ -676,7 +676,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
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struct radv_image_view *dest_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
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struct radv_image_view *dest_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
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struct radv_image *dst_img = dest_iview->image;
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struct radv_image *dst_img = dest_iview->image;
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if (radv_image_has_dcc(dst_img)) {
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if (radv_dcc_enabled(dst_img, dest_iview->base_mip)) {
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VkImageSubresourceRange range = {
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VkImageSubresourceRange range = {
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.aspectMask = dest_iview->aspect_mask,
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.aspectMask = dest_iview->aspect_mask,
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.baseMipLevel = dest_iview->base_mip,
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.baseMipLevel = dest_iview->base_mip,
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