ac/surface: gfx11 changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
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85c76518c9
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@ -1371,9 +1371,19 @@ static int gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, const struct rad
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sin.resourceType = in->resourceType;
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sin.resourceType = in->resourceType;
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sin.format = in->format;
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sin.format = in->format;
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sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
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sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
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/* TODO: We could allow some of these: */
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/* TODO: We could allow some of these: */
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sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
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sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
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if (info->chip_class >= GFX11) {
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if ((1 << G_0098F8_NUM_PIPES(info->gb_addr_config)) <= 16) {
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sin.forbiddenBlock.gfx11.thin256KB = 1;
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sin.forbiddenBlock.gfx11.thick256KB = 1;
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}
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} else {
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sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
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sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
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}
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sin.bpp = in->bpp;
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sin.bpp = in->bpp;
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sin.width = in->width;
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sin.width = in->width;
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sin.height = in->height;
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sin.height = in->height;
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@ -1394,6 +1404,10 @@ static int gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, const struct rad
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if (sin.flags.prt) {
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if (sin.flags.prt) {
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sin.forbiddenBlock.macroThin4KB = 1;
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sin.forbiddenBlock.macroThin4KB = 1;
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sin.forbiddenBlock.macroThick4KB = 1;
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sin.forbiddenBlock.macroThick4KB = 1;
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if (info->chip_class >= GFX11) {
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sin.forbiddenBlock.gfx11.thin256KB = 1;
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sin.forbiddenBlock.gfx11.thick256KB = 1;
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}
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sin.forbiddenBlock.linear = 1;
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sin.forbiddenBlock.linear = 1;
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}
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}
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@ -1437,6 +1451,10 @@ static int gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, const struct rad
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static bool is_dcc_supported_by_CB(const struct radeon_info *info, unsigned sw_mode)
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static bool is_dcc_supported_by_CB(const struct radeon_info *info, unsigned sw_mode)
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{
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{
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if (info->chip_class >= GFX11)
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return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X ||
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sw_mode == ADDR_SW_256KB_Z_X || sw_mode == ADDR_SW_256KB_R_X;
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if (info->chip_class >= GFX10)
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if (info->chip_class >= GFX10)
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return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X;
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return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X;
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@ -1543,6 +1561,7 @@ static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
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return true;
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return true;
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case GFX10:
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case GFX10:
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case GFX10_3:
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case GFX10_3:
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case GFX11:
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/* DCN requires INDEPENDENT_128B_BLOCKS = 0 only on Navi1x. */
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/* DCN requires INDEPENDENT_128B_BLOCKS = 0 only on Navi1x. */
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if (info->chip_class == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks)
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if (info->chip_class == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks)
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return false;
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return false;
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@ -1938,8 +1957,9 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
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}
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}
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}
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}
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/* FMASK */
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/* FMASK (it doesn't exist on GFX11) */
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if (in->numSamples > 1 && info->has_graphics && !(surf->flags & RADEON_SURF_NO_FMASK)) {
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if (info->chip_class <= GFX10_3 && info->has_graphics &&
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in->numSamples > 1 && !(surf->flags & RADEON_SURF_NO_FMASK)) {
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ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
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ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
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ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
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ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
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@ -1993,8 +2013,9 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
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}
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}
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}
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}
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/* CMASK -- on GFX10 only for FMASK */
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/* CMASK -- on GFX10 only for FMASK (and it doesn't exist on GFX11) */
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if (in->swizzleMode != ADDR_SW_LINEAR && in->resourceType == ADDR_RSRC_TEX_2D &&
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if (info->chip_class <= GFX10_3 && info->has_graphics &&
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in->swizzleMode != ADDR_SW_LINEAR && in->resourceType == ADDR_RSRC_TEX_2D &&
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((info->chip_class <= GFX9 && in->numSamples == 1 && in->flags.metaPipeUnaligned == 0 &&
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((info->chip_class <= GFX9 && in->numSamples == 1 && in->flags.metaPipeUnaligned == 0 &&
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in->flags.metaRbUnaligned == 0) ||
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in->flags.metaRbUnaligned == 0) ||
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(surf->fmask_size && in->numSamples >= 2))) {
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(surf->fmask_size && in->numSamples >= 2))) {
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@ -2348,6 +2369,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
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case ADDR_SW_64KB_S_T:
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case ADDR_SW_64KB_S_T:
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case ADDR_SW_4KB_S_X:
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case ADDR_SW_4KB_S_X:
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case ADDR_SW_64KB_S_X:
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case ADDR_SW_64KB_S_X:
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case ADDR_SW_256KB_S_X:
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surf->micro_tile_mode = RADEON_MICRO_MODE_STANDARD;
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surf->micro_tile_mode = RADEON_MICRO_MODE_STANDARD;
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break;
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break;
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@ -2359,6 +2381,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
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case ADDR_SW_64KB_D_T:
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case ADDR_SW_64KB_D_T:
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case ADDR_SW_4KB_D_X:
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case ADDR_SW_4KB_D_X:
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case ADDR_SW_64KB_D_X:
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case ADDR_SW_64KB_D_X:
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case ADDR_SW_256KB_D_X:
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surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
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surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
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break;
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break;
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@ -2369,7 +2392,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
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case ADDR_SW_64KB_R_T:
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case ADDR_SW_64KB_R_T:
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case ADDR_SW_4KB_R_X:
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case ADDR_SW_4KB_R_X:
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case ADDR_SW_64KB_R_X:
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case ADDR_SW_64KB_R_X:
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case ADDR_SW_VAR_R_X:
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case ADDR_SW_256KB_R_X:
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/* The rotated micro tile mode doesn't work if both CMASK and RB+ are
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/* The rotated micro tile mode doesn't work if both CMASK and RB+ are
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* used at the same time. We currently do not use rotated
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* used at the same time. We currently do not use rotated
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* in gfx9.
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* in gfx9.
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@ -2384,7 +2407,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
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case ADDR_SW_64KB_Z_T:
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case ADDR_SW_64KB_Z_T:
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case ADDR_SW_4KB_Z_X:
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case ADDR_SW_4KB_Z_X:
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case ADDR_SW_64KB_Z_X:
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case ADDR_SW_64KB_Z_X:
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case ADDR_SW_VAR_Z_X:
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case ADDR_SW_256KB_Z_X:
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surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
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surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
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break;
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break;
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@ -2692,6 +2715,7 @@ bool ac_surface_set_umd_metadata(const struct radeon_info *info, struct radeon_s
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case GFX10:
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case GFX10:
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case GFX10_3:
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case GFX10_3:
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case GFX11:
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surf->meta_offset =
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surf->meta_offset =
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((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc[6]) << 8) | ((uint64_t)desc[7] << 16);
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((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc[6]) << 8) | ((uint64_t)desc[7] << 16);
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surf->u.gfx9.color.dcc.pipe_aligned = G_00A018_META_PIPE_ALIGNED(desc[6]);
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surf->u.gfx9.color.dcc.pipe_aligned = G_00A018_META_PIPE_ALIGNED(desc[6]);
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@ -2733,6 +2757,7 @@ void ac_surface_get_umd_metadata(const struct radeon_info *info, struct radeon_s
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break;
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break;
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case GFX10:
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case GFX10:
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case GFX10_3:
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case GFX10_3:
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case GFX11:
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desc[6] &= C_00A018_META_DATA_ADDRESS_LO;
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desc[6] &= C_00A018_META_DATA_ADDRESS_LO;
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desc[6] |= S_00A018_META_DATA_ADDRESS_LO(surf->meta_offset >> 8);
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desc[6] |= S_00A018_META_DATA_ADDRESS_LO(surf->meta_offset >> 8);
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desc[7] = surf->meta_offset >> 16;
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desc[7] = surf->meta_offset >> 16;
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@ -2788,7 +2813,8 @@ static uint32_t ac_surface_get_gfx9_pitch_align(struct radeon_surf *surf)
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case ADDR_SW_64KB_Z_T:
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case ADDR_SW_64KB_Z_T:
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case ADDR_SW_64KB_Z_X:
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case ADDR_SW_64KB_Z_X:
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return 256 >> bpe_shift;
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return 256 >> bpe_shift;
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case ADDR_SW_VAR_Z_X:
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case ADDR_SW_256KB_Z_X:
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return 512 >> bpe_shift;
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default:
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default:
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return 1; /* TODO */
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return 1; /* TODO */
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}
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}
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