diff --git a/src/mesa/drivers/dri/i965/brw_program.h b/src/mesa/drivers/dri/i965/brw_program.h index 317fbe2b9f4..eed07a2c1c0 100644 --- a/src/mesa/drivers/dri/i965/brw_program.h +++ b/src/mesa/drivers/dri/i965/brw_program.h @@ -61,10 +61,12 @@ void brw_dump_ir(const char *stage, struct gl_shader_program *shader_prog, struct gl_linked_shader *shader, struct gl_program *prog); -void brw_upload_tcs_prog(struct brw_context *brw, - uint64_t per_vertex_slots, uint32_t per_patch_slots); -void brw_upload_tes_prog(struct brw_context *brw, - uint64_t per_vertex_slots, uint32_t per_patch_slots); +void brw_upload_tcs_prog(struct brw_context *brw); +void brw_tcs_populate_key(struct brw_context *brw, + struct brw_tcs_prog_key *key); +void brw_upload_tes_prog(struct brw_context *brw); +void brw_tes_populate_key(struct brw_context *brw, + struct brw_tes_prog_key *key); #ifdef __cplusplus } /* extern "C" */ diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 60f3be66a2c..8ce6851814b 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -682,22 +682,8 @@ static inline void brw_upload_tess_programs(struct brw_context *brw) { if (brw->tess_eval_program) { - uint64_t per_vertex_slots = brw->tess_eval_program->Base.InputsRead; - uint32_t per_patch_slots = - brw->tess_eval_program->Base.PatchInputsRead; - - /* The TCS may have additional outputs which aren't read by the - * TES (possibly for cross-thread communication). These need to - * be stored in the Patch URB Entry as well. - */ - if (brw->tess_ctrl_program) { - per_vertex_slots |= brw->tess_ctrl_program->Base.OutputsWritten; - per_patch_slots |= - brw->tess_ctrl_program->Base.PatchOutputsWritten; - } - - brw_upload_tcs_prog(brw, per_vertex_slots, per_patch_slots); - brw_upload_tes_prog(brw, per_vertex_slots, per_patch_slots); + brw_upload_tcs_prog(brw); + brw_upload_tes_prog(brw); } else { brw->tcs.prog_data = NULL; brw->tcs.base.prog_data = NULL; diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c index 7e6c69adb2c..d62ad662b49 100644 --- a/src/mesa/drivers/dri/i965/brw_tcs.c +++ b/src/mesa/drivers/dri/i965/brw_tcs.c @@ -312,14 +312,53 @@ brw_codegen_tcs_prog(struct brw_context *brw, return true; } +void +brw_tcs_populate_key(struct brw_context *brw, + struct brw_tcs_prog_key *key) +{ + uint64_t per_vertex_slots = brw->tess_eval_program->Base.InputsRead; + uint32_t per_patch_slots = brw->tess_eval_program->Base.PatchInputsRead; + + struct brw_tess_ctrl_program *tcp = + (struct brw_tess_ctrl_program *) brw->tess_ctrl_program; + struct brw_tess_eval_program *tep = + (struct brw_tess_eval_program *) brw->tess_eval_program; + struct gl_program *prog = &tcp->program.Base; + + memset(key, 0, sizeof(*key)); + + if (brw->tess_ctrl_program) { + per_vertex_slots |= brw->tess_ctrl_program->Base.OutputsWritten; + per_patch_slots |= brw->tess_ctrl_program->Base.PatchOutputsWritten; + } + + if (brw->gen < 8 || !tcp) + key->input_vertices = brw->ctx.TessCtrlProgram.patch_vertices; + key->outputs_written = per_vertex_slots; + key->patch_outputs_written = per_patch_slots; + + /* We need to specialize our code generation for tessellation levels + * based on the domain the DS is expecting to tessellate. + */ + key->tes_primitive_mode = tep->program.PrimitiveMode; + key->quads_workaround = brw->gen < 9 && + tep->program.PrimitiveMode == GL_QUADS && + tep->program.Spacing == GL_EQUAL; + + if (tcp) { + key->program_string_id = tcp->id; + + /* _NEW_TEXTURE */ + brw_populate_sampler_prog_key_data(&brw->ctx, prog, &key->tex); + } else { + key->outputs_written = tep->program.Base.InputsRead; + } +} void -brw_upload_tcs_prog(struct brw_context *brw, - uint64_t per_vertex_slots, - uint32_t per_patch_slots) +brw_upload_tcs_prog(struct brw_context *brw) { - struct gl_context *ctx = &brw->ctx; - struct gl_shader_program **current = ctx->_Shader->CurrentProgram; + struct gl_shader_program **current = brw->ctx._Shader->CurrentProgram; struct brw_stage_state *stage_state = &brw->tcs.base; struct brw_tcs_prog_key key; /* BRW_NEW_TESS_PROGRAMS */ @@ -335,32 +374,7 @@ brw_upload_tcs_prog(struct brw_context *brw, BRW_NEW_TESS_PROGRAMS)) return; - struct gl_program *prog = &tcp->program.Base; - - memset(&key, 0, sizeof(key)); - - if (brw->gen < 8 || !tcp) - key.input_vertices = ctx->TessCtrlProgram.patch_vertices; - key.outputs_written = per_vertex_slots; - key.patch_outputs_written = per_patch_slots; - - /* We need to specialize our code generation for tessellation levels - * based on the domain the DS is expecting to tessellate. - */ - key.tes_primitive_mode = tep->program.PrimitiveMode; - key.quads_workaround = brw->gen < 9 && - tep->program.PrimitiveMode == GL_QUADS && - tep->program.Spacing == GL_EQUAL; - - if (tcp) { - key.program_string_id = tcp->id; - - /* _NEW_TEXTURE */ - brw_populate_sampler_prog_key_data(ctx, prog, &key.tex); - } else { - key.outputs_written = tep->program.Base.InputsRead; - } - + brw_tcs_populate_key(brw, &key); if (!brw_search_cache(&brw->cache, BRW_CACHE_TCS_PROG, &key, sizeof(key), diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c index 87ada174e82..ffd5702af54 100644 --- a/src/mesa/drivers/dri/i965/brw_tes.c +++ b/src/mesa/drivers/dri/i965/brw_tes.c @@ -229,14 +229,47 @@ brw_codegen_tes_prog(struct brw_context *brw, return true; } +void +brw_tes_populate_key(struct brw_context *brw, + struct brw_tes_prog_key *key) +{ + + uint64_t per_vertex_slots = brw->tess_eval_program->Base.InputsRead; + uint32_t per_patch_slots = brw->tess_eval_program->Base.PatchInputsRead; + + struct brw_tess_eval_program *tep = + (struct brw_tess_eval_program *) brw->tess_eval_program; + struct gl_program *prog = &tep->program.Base; + + memset(key, 0, sizeof(*key)); + + key->program_string_id = tep->id; + + /* The TCS may have additional outputs which aren't read by the + * TES (possibly for cross-thread communication). These need to + * be stored in the Patch URB Entry as well. + */ + if (brw->tess_ctrl_program) { + per_vertex_slots |= brw->tess_ctrl_program->Base.OutputsWritten; + per_patch_slots |= brw->tess_ctrl_program->Base.PatchOutputsWritten; + } + + /* Ignore gl_TessLevelInner/Outer - we treat them as system values, + * not inputs, and they're always present in the URB entry regardless + * of whether or not we read them. + */ + key->inputs_read = per_vertex_slots & + ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER); + key->patch_inputs_read = per_patch_slots; + + /* _NEW_TEXTURE */ + brw_populate_sampler_prog_key_data(&brw->ctx, prog, &key->tex); +} void -brw_upload_tes_prog(struct brw_context *brw, - uint64_t per_vertex_slots, - uint32_t per_patch_slots) +brw_upload_tes_prog(struct brw_context *brw) { - struct gl_context *ctx = &brw->ctx; - struct gl_shader_program **current = ctx->_Shader->CurrentProgram; + struct gl_shader_program **current = brw->ctx._Shader->CurrentProgram; struct brw_stage_state *stage_state = &brw->tes.base; struct brw_tes_prog_key key; /* BRW_NEW_TESS_PROGRAMS */ @@ -248,22 +281,7 @@ brw_upload_tes_prog(struct brw_context *brw, BRW_NEW_TESS_PROGRAMS)) return; - struct gl_program *prog = &tep->program.Base; - - memset(&key, 0, sizeof(key)); - - key.program_string_id = tep->id; - - /* Ignore gl_TessLevelInner/Outer - we treat them as system values, - * not inputs, and they're always present in the URB entry regardless - * of whether or not we read them. - */ - key.inputs_read = per_vertex_slots & - ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER); - key.patch_inputs_read = per_patch_slots; - - /* _NEW_TEXTURE */ - brw_populate_sampler_prog_key_data(ctx, prog, &key.tex); + brw_tes_populate_key(brw, &key); if (!brw_search_cache(&brw->cache, BRW_CACHE_TES_PROG, &key, sizeof(key),