i965/gen7: Use the generic ISL-based path for texture surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
This commit is contained in:
Jason Ekstrand
parent
26282a01f5
commit
8521ce1a7e
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@ -39,27 +39,6 @@
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#include "brw_defines.h"
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#include "brw_wm.h"
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/**
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* Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
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* "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
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*
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* SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
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* 0 1 2 3 4 5
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* 4 5 6 7 0 1
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* SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
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*
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* which is simply adding 4 then modding by 8 (or anding with 7).
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*
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* We then may need to apply workarounds for textureGather hardware bugs.
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*/
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static unsigned
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swizzle_to_scs(GLenum swizzle, bool need_green_to_blue)
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{
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unsigned scs = (swizzle + 4) & 7;
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return (need_green_to_blue && scs == HSW_SCS_GREEN) ? HSW_SCS_BLUE : scs;
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}
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uint32_t
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gen7_surface_tiling_mode(uint32_t tiling)
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{
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@ -264,150 +243,6 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
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gen7_check_surface_setup(surf, false /* is_render_target */);
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}
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static void
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gen7_emit_texture_surface_state(struct brw_context *brw,
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struct intel_mipmap_tree *mt,
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GLenum target,
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unsigned min_layer, unsigned max_layer,
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unsigned min_level, unsigned max_level,
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unsigned format,
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unsigned swizzle,
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uint32_t *surf_offset,
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int surf_index /* unused */,
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bool rw, bool for_gather)
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{
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const unsigned depth = max_layer - min_layer;
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uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
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8 * 4, 32, surf_offset);
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memset(surf, 0, 8 * 4);
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surf[0] = translate_tex_target(target) << BRW_SURFACE_TYPE_SHIFT |
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format << BRW_SURFACE_FORMAT_SHIFT |
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gen7_surface_tiling_mode(mt->tiling);
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/* mask of faces present in cube map; for other surfaces MBZ. */
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if (target == GL_TEXTURE_CUBE_MAP || target == GL_TEXTURE_CUBE_MAP_ARRAY)
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surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
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if (mt->valign == 4)
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surf[0] |= GEN7_SURFACE_VALIGN_4;
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if (mt->halign == 8)
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surf[0] |= GEN7_SURFACE_HALIGN_8;
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if (mt->target != GL_TEXTURE_3D)
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surf[0] |= GEN7_SURFACE_IS_ARRAY;
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if (mt->array_layout == ALL_SLICES_AT_EACH_LOD)
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surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
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surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
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surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
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SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
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surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
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(mt->pitch - 1);
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if (brw->is_haswell && _mesa_is_format_integer(mt->format))
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surf[3] |= HSW_SURFACE_IS_INTEGER_FORMAT;
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surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
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SET_FIELD(min_layer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
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SET_FIELD(depth - 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
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surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
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SET_FIELD(min_level - mt->first_level, GEN7_SURFACE_MIN_LOD) |
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/* mip count */
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(max_level - min_level - 1));
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surf[7] = mt->fast_clear_color_value;
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if (brw->is_haswell) {
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const bool need_scs_green_to_blue = for_gather && format == BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
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surf[7] |=
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SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0), need_scs_green_to_blue), GEN7_SURFACE_SCS_R) |
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SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1), need_scs_green_to_blue), GEN7_SURFACE_SCS_G) |
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SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2), need_scs_green_to_blue), GEN7_SURFACE_SCS_B) |
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SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3), need_scs_green_to_blue), GEN7_SURFACE_SCS_A);
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}
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if (mt->mcs_mt) {
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gen7_set_surface_mcs_info(brw, surf, *surf_offset,
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mt->mcs_mt, false /* is RT */);
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}
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/* Emit relocation to surface contents */
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drm_intel_bo_emit_reloc(brw->batch.bo,
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*surf_offset + 4,
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mt->bo,
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surf[1] - mt->bo->offset64,
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I915_GEM_DOMAIN_SAMPLER,
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(rw ? I915_GEM_DOMAIN_SAMPLER : 0));
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gen7_check_surface_setup(surf, false /* is_render_target */);
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}
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static void
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gen7_update_texture_surface(struct gl_context *ctx,
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unsigned unit,
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uint32_t *surf_offset,
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bool for_gather,
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uint32_t plane)
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{
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struct brw_context *brw = brw_context(ctx);
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struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current;
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if (obj->Target == GL_TEXTURE_BUFFER) {
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brw_update_buffer_texture_surface(ctx, unit, surf_offset);
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} else {
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struct intel_texture_object *intel_obj = intel_texture_object(obj);
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struct intel_mipmap_tree *mt = intel_obj->mt;
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if (plane > 0) {
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if (mt->plane[plane - 1] == NULL)
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return;
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mt = mt->plane[plane - 1];
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}
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struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
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/* If this is a view with restricted NumLayers, then our effective depth
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* is not just the miptree depth.
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*/
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const unsigned depth = (obj->Immutable && obj->Target != GL_TEXTURE_3D ?
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obj->NumLayers : mt->logical_depth0);
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/* Handling GL_ALPHA as a surface format override breaks 1.30+ style
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* texturing functions that return a float, as our code generation always
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* selects the .x channel (which would always be 0).
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*/
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struct gl_texture_image *firstImage = obj->Image[0][obj->BaseLevel];
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const bool alpha_depth = obj->DepthMode == GL_ALPHA &&
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(firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
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firstImage->_BaseFormat == GL_DEPTH_STENCIL);
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const unsigned swizzle = (unlikely(alpha_depth) ? SWIZZLE_XYZW :
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brw_get_texture_swizzle(&brw->ctx, obj));
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mesa_format mesa_fmt = plane == 0 ? intel_obj->_Format : mt->format;
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unsigned format = translate_tex_format(brw, mesa_fmt,
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sampler->sRGBDecode);
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if (for_gather && format == BRW_SURFACEFORMAT_R32G32_FLOAT)
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format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
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const int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
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gen7_emit_texture_surface_state(brw, mt, obj->Target,
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obj->MinLayer, obj->MinLayer + depth,
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obj->MinLevel + obj->BaseLevel,
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obj->MinLevel + intel_obj->_MaxLevel + 1,
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format, swizzle, surf_offset,
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surf_index, false, for_gather);
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}
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}
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/**
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* Creates a null surface.
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*
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@ -578,9 +413,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
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void
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gen7_init_vtable_surface_functions(struct brw_context *brw)
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{
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brw->vtbl.update_texture_surface = gen7_update_texture_surface;
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brw->vtbl.update_texture_surface = brw_update_texture_surface;
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brw->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
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brw->vtbl.emit_null_surface_state = gen7_emit_null_surface_state;
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brw->vtbl.emit_texture_surface_state = gen7_emit_texture_surface_state;
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brw->vtbl.emit_buffer_surface_state = gen7_emit_buffer_surface_state;
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}
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