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i965/vec4: Handle nir_tex_src_ms_index more like the scalar 

v2: Rebase on top of f9a9ba5e.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
This commit is contained in:
Ian Romanick 2015-11-17 19:31:39 -08:00
parent 457bb290ef
commit 84b6c64efc
1 changed files with 10 additions and 8 deletions
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18
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
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@ -1654,14 +1654,6 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
case nir_tex_src_ms_index: {
sample_index = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 1);
assert(coord_type != NULL);
if (devinfo->gen >= 7 &&
key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
mcs = emit_mcs_fetch(coord_type, coordinate, sampler_reg);
} else {
mcs = brw_imm_ud(0u);
}
mcs = retype(mcs, BRW_REGISTER_TYPE_UD);
break;
}
@ -1703,6 +1695,16 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
}
}
if (instr->op == nir_texop_txf_ms) {
assert(coord_type != NULL);
if (devinfo->gen >= 7 &&
key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
mcs = emit_mcs_fetch(coord_type, coordinate, sampler_reg);
} else {
mcs = brw_imm_ud(0u);
}
}
uint32_t constant_offset = 0;
for (unsigned i = 0; i < 3; i++) {
if (instr->const_offset[i] != 0) {