i965: Require pixel alignment for GPU copy blit
The blitter will start at a pixel's natural alignment. For PBOs, if the provided offset if not aligned, bits will get dropped. This change adds offset alignment check for src and dst, kicking back if the requirements are not met. The change is based on following verbiage from BSPEC: Color pixel sizes supported are 8, 16, and 32 bits per pixel (bpp). All pixels are naturally aligned. Found in the following locations: page 35 of intel-gfx-prm-osrc-hsw-blitter.pdf page 29 of ivb_ihd_os_vol1_part4.pdf page 29 of snb_ihd_os_vol1_part5.pdf This behavior was observed with Steam Big Picture rendering incorrect icon colors. The fix has been tested on Ubuntu and SteamOS on Haswell. Signed-off-by: Cody Northrop <cody@lunarg.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83908 Reviewed-by: Neil Roberts <neil@linux.intel.com>
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@ -271,9 +271,10 @@ intelEmitCopyBlit(struct intel_context *intel,
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dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
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/* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
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* the low bits.
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* the low bits. Offsets must be naturally aligned.
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*/
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if (src_pitch % 4 != 0 || dst_pitch % 4 != 0)
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if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
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dst_pitch % 4 != 0 || dst_offset % cpp != 0)
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return false;
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/* For big formats (such as floating point), do the copy using 16 or 32bpp
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@ -344,9 +344,10 @@ intelEmitCopyBlit(struct brw_context *brw,
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dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
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/* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
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* the low bits.
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* the low bits. Offsets must be naturally aligned.
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*/
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if (src_pitch % 4 != 0 || dst_pitch % 4 != 0)
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if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
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dst_pitch % 4 != 0 || dst_offset % cpp != 0)
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return false;
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/* For big formats (such as floating point), do the copy using 16 or 32bpp
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