pan/va: Fix conservative branch handling
Mixed up lanes and conservative branch combine. Fix that. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15069>
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@ -280,7 +280,7 @@
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<value>b3</value>
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</enum>
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<enum name="Lane (32-bit)">
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<enum name="Combine">
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<desc>
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Used for the lane select of `BRANCHZ`. To use an 8-bit condition, a
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separate `ICMP` is required to cast to 16-bit.
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@ -288,7 +288,8 @@
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<value default="true">none</value>
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<value>h0</value>
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<value>h1</value>
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<reserved/>
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<value>and</value>
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<value>lowbits</value>
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</enum>
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<enum name="Lane (16-bit)" implied="true">
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@ -661,8 +662,9 @@
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source to a nonzero constant to implement a jump. May introduce
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divergence, so generally requires `.reconverge` flow control.
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</desc>
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<src lane="37">Value to compare against zero</src>
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<src combine="true">Value to compare against zero</src>
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<imm name="offset" start="8" size="27" signed="true"/>
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<conservative/>
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<mod name="eq" start="36" size="1"/>
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</ins>
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@ -683,8 +685,9 @@
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Jump to an indirectly specified (absolute or relative) address. Used to
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jump to blend shaders at the end of a fragment shader.
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</desc>
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<src>Value to compare against zero</src>
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<src combine="true">Value to compare against zero</src>
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<src>Branch target</src>
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<conservative/>
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<mod name="eq" start="36" size="1"/>
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<mod name="absolute" start="40" size="1"/>
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</ins>
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@ -275,6 +275,11 @@ def parse_asm(line):
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swizzled = True
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val = enums[f'lane_{src.size}_bit'].bare_values.index(mod)
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encoded |= (val << src.offset['lane'])
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elif src.combine and mod in enums['combine'].bare_values:
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die_if(swizzled, "Multiple swizzles specified")
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swizzled = True
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val = enums['combine'].bare_values.index(mod)
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encoded |= (val << src.offset['combine'])
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elif src.size == 32 and mod in enums['widen'].bare_values:
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die_if(not src.swizzle, "Instruction doesn't take widens")
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die_if(swizzled, "Multiple swizzles specified")
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@ -189,6 +189,8 @@ va_disasm_instr(FILE *fp, uint64_t instr)
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fputs(valhall_half_swizzles_8_bit[(instr >> ${src.offset['widen']}) & 0xF], fp);
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% elif src.widen:
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fputs(valhall_swizzles_${src.size}_bit[(instr >> ${src.offset['widen']}) & 0xF], fp);
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% elif src.combine:
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fputs(valhall_combine[(instr >> ${src.offset['combine']}) & 0x7], fp);
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% endif
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% if src.lane:
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fputs(valhall_lane_${src.size}_bit[(instr >> ${src.lane}) & 0x3], fp);
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@ -98,7 +98,8 @@ def Flag(name, start):
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# Model a single instruction
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class Source:
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def __init__(self, index, size, is_float = False, swizzle = False, halfswizzle = False, widen = False, lanes = False, lane = None, absneg = False, notted = False, name = ""):
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def __init__(self, index, size, is_float = False, swizzle = False,
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halfswizzle = False, widen = False, lanes = False, combine = False, lane = None, absneg = False, notted = False, name = ""):
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self.is_float = is_float or absneg
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self.size = size
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self.absneg = absneg
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@ -108,6 +109,7 @@ class Source:
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self.widen = widen
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self.lanes = lanes
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self.lane = lane
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self.combine = combine
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self.name = name
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self.offset = {}
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@ -130,6 +132,9 @@ class Source:
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assert(size in [16, 32])
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self.offset['swizzle'] = 24 + ((2 - index) * 2)
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self.bits['swizzle'] = 2
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if combine:
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self.offset['combine'] = 37
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self.bits['combine'] = 3
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class Dest:
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def __init__(self, name = ""):
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@ -215,6 +220,7 @@ def build_source(el, i, size):
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halfswizzle = el.get('halfswizzle', False),
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widen = el.get('widen', False),
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lanes = el.get('lanes', False),
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combine = el.get('combine', False),
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lane = lane,
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notted = el.get('not', False),
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name = el.text or "")
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@ -354,6 +360,7 @@ MODIFIERS = {
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"clamp": Modifier("clamp", 32, 2),
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"sr_count": Modifier("staging_register_count", 33, 3, implied = True),
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"conservative": Flag("conservative", 35),
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"subgroup": Modifier("subgroup_size", 36, 4),
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"update": Modifier("update_mode", 36, 2),
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"sample": Modifier("sample_mode", 38, 2),
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