intel, anv: propagate robustness setting to nir_opt_load_store_vectorize
Closes #4309 Fixes dEQP-VK-robustness.robustness2.*.readonly.* Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10147>
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@ -256,6 +256,8 @@ struct brw_base_prog_key {
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enum brw_subgroup_size_type subgroup_size_type;
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struct brw_sampler_prog_key_data tex;
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bool robust_buffer_access;
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};
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/**
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@ -9097,7 +9097,8 @@ brw_compile_fs(const struct brw_compiler *compiler,
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if (!key->multisample_fbo)
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NIR_PASS_V(nir, brw_nir_demote_sample_qualifiers);
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NIR_PASS_V(nir, brw_nir_move_interpolation_to_top);
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brw_postprocess_nir(nir, compiler, true, debug_enabled);
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brw_postprocess_nir(nir, compiler, true, debug_enabled,
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key->base.robust_buffer_access);
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brw_nir_populate_wm_prog_data(nir, compiler->devinfo, key, prog_data);
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@ -9427,7 +9428,8 @@ compile_cs_to_nir(const struct brw_compiler *compiler,
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NIR_PASS_V(shader, nir_opt_constant_folding);
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NIR_PASS_V(shader, nir_opt_dce);
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brw_postprocess_nir(shader, compiler, true, debug_enabled);
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brw_postprocess_nir(shader, compiler, true, debug_enabled,
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key->base.robust_buffer_access);
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return shader;
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}
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@ -9720,7 +9722,8 @@ brw_compile_bs(const struct brw_compiler *compiler, void *log_data,
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const unsigned max_dispatch_width = 16;
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brw_nir_apply_key(shader, compiler, &key->base, max_dispatch_width, true);
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brw_postprocess_nir(shader, compiler, true, debug_enabled);
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brw_postprocess_nir(shader, compiler, true, debug_enabled,
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key->base.robust_buffer_access);
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fs_visitor *v = NULL, *v8 = NULL, *v16 = NULL;
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bool has_spilled = false;
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@ -1027,7 +1027,8 @@ bool combine_all_barriers(nir_intrinsic_instr *a,
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static void
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brw_vectorize_lower_mem_access(nir_shader *nir,
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const struct brw_compiler *compiler,
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bool is_scalar)
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bool is_scalar,
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bool robust_buffer_access)
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{
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const struct gen_device_info *devinfo = compiler->devinfo;
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bool progress = false;
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@ -1040,6 +1041,11 @@ brw_vectorize_lower_mem_access(nir_shader *nir,
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.robust_modes = (nir_variable_mode)0,
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};
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if (robust_buffer_access) {
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options.robust_modes = nir_var_mem_ubo | nir_var_mem_ssbo |
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nir_var_mem_global;
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}
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OPT(nir_opt_load_store_vectorize, &options);
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}
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@ -1077,7 +1083,8 @@ nir_shader_has_local_variables(const nir_shader *nir)
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*/
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void
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brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
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bool is_scalar, bool debug_enabled)
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bool is_scalar, bool debug_enabled,
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bool robust_buffer_access)
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{
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const struct gen_device_info *devinfo = compiler->devinfo;
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@ -1103,7 +1110,8 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
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brw_nir_optimize(nir, compiler, is_scalar, false);
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}
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brw_vectorize_lower_mem_access(nir, compiler, is_scalar);
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brw_vectorize_lower_mem_access(nir, compiler, is_scalar,
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robust_buffer_access);
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if (OPT(nir_lower_int64))
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brw_nir_optimize(nir, compiler, is_scalar, false);
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@ -135,7 +135,8 @@ bool brw_nir_lower_mem_access_bit_sizes(nir_shader *shader,
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void brw_postprocess_nir(nir_shader *nir,
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const struct brw_compiler *compiler,
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bool is_scalar,
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bool debug_enabled);
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bool debug_enabled,
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bool robust_buffer_access);
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bool brw_nir_clamp_image_1d_2d_array_sizes(nir_shader *shader);
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@ -1324,7 +1324,8 @@ brw_compile_tes(const struct brw_compiler *compiler,
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brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
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brw_nir_lower_tes_inputs(nir, input_vue_map);
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brw_nir_lower_vue_outputs(nir);
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brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled);
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brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled,
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key->base.robust_buffer_access);
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brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
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nir->info.outputs_written,
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@ -2867,7 +2867,8 @@ brw_compile_vs(const struct brw_compiler *compiler,
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brw_nir_lower_vs_inputs(nir, key->gl_attrib_wa_flags);
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brw_nir_lower_vue_outputs(nir);
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brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled);
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brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled,
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key->base.robust_buffer_access);
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prog_data->base.clip_distance_mask =
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((1 << nir->info.clip_distance_array_size) - 1);
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@ -618,7 +618,8 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
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brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
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brw_nir_lower_vue_inputs(nir, &c.input_vue_map);
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brw_nir_lower_vue_outputs(nir);
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brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled);
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brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled,
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key->base.robust_buffer_access);
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prog_data->base.clip_distance_mask =
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((1 << nir->info.clip_distance_array_size) - 1);
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@ -390,7 +390,8 @@ brw_compile_tcs(const struct brw_compiler *compiler,
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if (key->quads_workaround)
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brw_nir_apply_tcs_quads_workaround(nir);
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brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled);
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brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled,
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key->base.robust_buffer_access);
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bool has_primitive_id =
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BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
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@ -394,6 +394,7 @@ populate_sampler_prog_key(const struct gen_device_info *devinfo,
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static void
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populate_base_prog_key(const struct gen_device_info *devinfo,
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VkPipelineShaderStageCreateFlags flags,
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bool robust_buffer_acccess,
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struct brw_base_prog_key *key)
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{
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if (flags & VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT)
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@ -401,17 +402,20 @@ populate_base_prog_key(const struct gen_device_info *devinfo,
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else
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key->subgroup_size_type = BRW_SUBGROUP_SIZE_API_CONSTANT;
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key->robust_buffer_access = robust_buffer_acccess;
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populate_sampler_prog_key(devinfo, &key->tex);
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}
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static void
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populate_vs_prog_key(const struct gen_device_info *devinfo,
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VkPipelineShaderStageCreateFlags flags,
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bool robust_buffer_acccess,
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struct brw_vs_prog_key *key)
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{
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memset(key, 0, sizeof(*key));
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populate_base_prog_key(devinfo, flags, &key->base);
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populate_base_prog_key(devinfo, flags, robust_buffer_acccess, &key->base);
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/* XXX: Handle vertex input work-arounds */
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@ -421,12 +425,13 @@ populate_vs_prog_key(const struct gen_device_info *devinfo,
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static void
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populate_tcs_prog_key(const struct gen_device_info *devinfo,
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VkPipelineShaderStageCreateFlags flags,
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bool robust_buffer_acccess,
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unsigned input_vertices,
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struct brw_tcs_prog_key *key)
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{
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memset(key, 0, sizeof(*key));
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populate_base_prog_key(devinfo, flags, &key->base);
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populate_base_prog_key(devinfo, flags, robust_buffer_acccess, &key->base);
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key->input_vertices = input_vertices;
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}
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@ -434,33 +439,36 @@ populate_tcs_prog_key(const struct gen_device_info *devinfo,
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static void
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populate_tes_prog_key(const struct gen_device_info *devinfo,
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VkPipelineShaderStageCreateFlags flags,
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bool robust_buffer_acccess,
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struct brw_tes_prog_key *key)
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{
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memset(key, 0, sizeof(*key));
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populate_base_prog_key(devinfo, flags, &key->base);
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populate_base_prog_key(devinfo, flags, robust_buffer_acccess, &key->base);
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}
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static void
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populate_gs_prog_key(const struct gen_device_info *devinfo,
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VkPipelineShaderStageCreateFlags flags,
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bool robust_buffer_acccess,
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struct brw_gs_prog_key *key)
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{
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memset(key, 0, sizeof(*key));
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populate_base_prog_key(devinfo, flags, &key->base);
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populate_base_prog_key(devinfo, flags, robust_buffer_acccess, &key->base);
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}
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static void
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populate_wm_prog_key(const struct gen_device_info *devinfo,
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VkPipelineShaderStageCreateFlags flags,
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bool robust_buffer_acccess,
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const struct anv_subpass *subpass,
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const VkPipelineMultisampleStateCreateInfo *ms_info,
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struct brw_wm_prog_key *key)
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{
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memset(key, 0, sizeof(*key));
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populate_base_prog_key(devinfo, flags, &key->base);
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populate_base_prog_key(devinfo, flags, robust_buffer_acccess, &key->base);
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/* We set this to 0 here and set to the actual value before we call
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* brw_compile_fs.
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@ -510,12 +518,13 @@ populate_wm_prog_key(const struct gen_device_info *devinfo,
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static void
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populate_cs_prog_key(const struct gen_device_info *devinfo,
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VkPipelineShaderStageCreateFlags flags,
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bool robust_buffer_acccess,
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const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *rss_info,
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struct brw_cs_prog_key *key)
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{
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memset(key, 0, sizeof(*key));
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populate_base_prog_key(devinfo, flags, &key->base);
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populate_base_prog_key(devinfo, flags, robust_buffer_acccess, &key->base);
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if (rss_info) {
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assert(key->base.subgroup_size_type != BRW_SUBGROUP_SIZE_VARYING);
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@ -1269,23 +1278,31 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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const struct gen_device_info *devinfo = &pipeline->base.device->info;
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switch (stage) {
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case MESA_SHADER_VERTEX:
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populate_vs_prog_key(devinfo, sinfo->flags, &stages[stage].key.vs);
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populate_vs_prog_key(devinfo, sinfo->flags,
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pipeline->base.device->robust_buffer_access,
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&stages[stage].key.vs);
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break;
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case MESA_SHADER_TESS_CTRL:
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populate_tcs_prog_key(devinfo, sinfo->flags,
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pipeline->base.device->robust_buffer_access,
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info->pTessellationState->patchControlPoints,
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&stages[stage].key.tcs);
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break;
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case MESA_SHADER_TESS_EVAL:
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populate_tes_prog_key(devinfo, sinfo->flags, &stages[stage].key.tes);
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populate_tes_prog_key(devinfo, sinfo->flags,
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pipeline->base.device->robust_buffer_access,
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&stages[stage].key.tes);
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break;
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case MESA_SHADER_GEOMETRY:
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populate_gs_prog_key(devinfo, sinfo->flags, &stages[stage].key.gs);
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populate_gs_prog_key(devinfo, sinfo->flags,
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pipeline->base.device->robust_buffer_access,
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&stages[stage].key.gs);
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break;
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case MESA_SHADER_FRAGMENT: {
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const bool raster_enabled =
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!info->pRasterizationState->rasterizerDiscardEnable;
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populate_wm_prog_key(devinfo, sinfo->flags,
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pipeline->base.device->robust_buffer_access,
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pipeline->subpass,
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raster_enabled ? info->pMultisampleState : NULL,
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&stages[stage].key.wm);
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@ -1662,6 +1679,7 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
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PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
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populate_cs_prog_key(&pipeline->base.device->info, info->stage.flags,
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pipeline->base.device->robust_buffer_access,
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rss_info, &stage.key.cs);
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ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
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