From 82d77f0ea85c459fb44423302458e70f748d2e4d Mon Sep 17 00:00:00 2001 From: Caio Marcelo de Oliveira Filho Date: Tue, 23 Mar 2021 11:12:40 -0700 Subject: [PATCH] intel/compiler: Refactor the shader INTEL_DEBUG checks Make the check once in a variable, that can be reused for other parts. Also add `unlikely` to the various conditionals depending on it Reviewed-by: Kenneth Graunke Reviewed-by: Jordan Justen Part-of: --- src/intel/compiler/brw_fs.cpp | 20 +++++++++++++------- src/intel/compiler/brw_shader.cpp | 7 ++++--- src/intel/compiler/brw_vec4.cpp | 5 +++-- src/intel/compiler/brw_vec4_gs_visitor.cpp | 5 +++-- src/intel/compiler/brw_vec4_tcs.cpp | 3 ++- 5 files changed, 25 insertions(+), 15 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 8b97c65d5ea..565102ce841 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -9063,6 +9063,7 @@ brw_compile_fs(const struct brw_compiler *compiler, const struct brw_wm_prog_key *key = params->key; struct brw_wm_prog_data *prog_data = params->prog_data; bool allow_spilling = params->allow_spilling; + const bool debug_enabled = INTEL_DEBUG & DEBUG_WM; prog_data->base.stage = MESA_SHADER_FRAGMENT; @@ -9238,7 +9239,7 @@ brw_compile_fs(const struct brw_compiler *compiler, fs_generator g(compiler, params->log_data, mem_ctx, &prog_data->base, v8->runtime_check_aads_emit, MESA_SHADER_FRAGMENT); - if (INTEL_DEBUG & DEBUG_WM) { + if (unlikely(debug_enabled)) { g.enable_debug(ralloc_asprintf(mem_ctx, "%s fragment shader %s", nir->info.label ? nir->info.label : "unnamed", @@ -9407,7 +9408,8 @@ compile_cs_to_nir(const struct brw_compiler *compiler, void *mem_ctx, const struct brw_cs_prog_key *key, const nir_shader *src_shader, - unsigned dispatch_width) + unsigned dispatch_width, + bool debug_enabled) { nir_shader *shader = nir_shader_clone(mem_ctx, src_shader); brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true); @@ -9433,6 +9435,8 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, struct brw_compile_stats *stats, char **error_str) { + const bool debug_enabled = INTEL_DEBUG & DEBUG_CS; + prog_data->base.stage = MESA_SHADER_COMPUTE; prog_data->base.total_shared = nir->info.cs.shared_size; @@ -9491,7 +9495,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, if (!(INTEL_DEBUG & DEBUG_NO8) && min_dispatch_width <= 8 && max_dispatch_width >= 8) { nir_shader *nir8 = compile_cs_to_nir(compiler, mem_ctx, key, - nir, 8); + nir, 8, debug_enabled); v8 = new fs_visitor(compiler, log_data, mem_ctx, &key->base, &prog_data->base, nir8, 8, shader_time_index); @@ -9517,7 +9521,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, min_dispatch_width <= 16 && max_dispatch_width >= 16) { /* Try a SIMD16 compile */ nir_shader *nir16 = compile_cs_to_nir(compiler, mem_ctx, key, - nir, 16); + nir, 16, debug_enabled); v16 = new fs_visitor(compiler, log_data, mem_ctx, &key->base, &prog_data->base, nir16, 16, shader_time_index); @@ -9565,7 +9569,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, min_dispatch_width <= 32 && max_dispatch_width >= 32) { /* Try a SIMD32 compile */ nir_shader *nir32 = compile_cs_to_nir(compiler, mem_ctx, key, - nir, 32); + nir, 32, debug_enabled); v32 = new fs_visitor(compiler, log_data, mem_ctx, &key->base, &prog_data->base, nir32, 32, shader_time_index); @@ -9614,7 +9618,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, fs_generator g(compiler, log_data, mem_ctx, &prog_data->base, v->runtime_check_aads_emit, MESA_SHADER_COMPUTE); - if (INTEL_DEBUG & DEBUG_CS) { + if (unlikely(debug_enabled)) { char *name = ralloc_asprintf(mem_ctx, "%s compute shader %s", nir->info.label ? nir->info.label : "unnamed", @@ -9710,6 +9714,8 @@ brw_compile_bs(const struct brw_compiler *compiler, void *log_data, struct brw_compile_stats *stats, char **error_str) { + const bool debug_enabled = INTEL_DEBUG & DEBUG_RT; + prog_data->base.stage = shader->info.stage; prog_data->stack_size = shader->scratch_size; @@ -9778,7 +9784,7 @@ brw_compile_bs(const struct brw_compiler *compiler, void *log_data, fs_generator g(compiler, log_data, mem_ctx, &prog_data->base, v->runtime_check_aads_emit, shader->info.stage); - if (INTEL_DEBUG & DEBUG_RT) { + if (unlikely(debug_enabled)) { char *name = ralloc_asprintf(mem_ctx, "%s %s shader %s", shader->info.label ? shader->info.label : "unnamed", diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 9a6aad85917..1c5d58791b1 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -1312,6 +1312,7 @@ brw_compile_tes(const struct brw_compiler *compiler, { const struct gen_device_info *devinfo = compiler->devinfo; const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL]; + const bool debug_enabled = INTEL_DEBUG & DEBUG_TES; const unsigned *assembly; prog_data->base.base.stage = MESA_SHADER_TESS_EVAL; @@ -1382,7 +1383,7 @@ brw_compile_tes(const struct brw_compiler *compiler, : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW; } - if (INTEL_DEBUG & DEBUG_TES) { + if (unlikely(debug_enabled)) { fprintf(stderr, "TES Input "); brw_print_vue_map(stderr, input_vue_map, MESA_SHADER_TESS_EVAL); fprintf(stderr, "TES Output "); @@ -1405,7 +1406,7 @@ brw_compile_tes(const struct brw_compiler *compiler, fs_generator g(compiler, log_data, mem_ctx, &prog_data->base.base, false, MESA_SHADER_TESS_EVAL); - if (INTEL_DEBUG & DEBUG_TES) { + if (unlikely(debug_enabled)) { g.enable_debug(ralloc_asprintf(mem_ctx, "%s tessellation evaluation shader %s", nir->info.label ? nir->info.label @@ -1428,7 +1429,7 @@ brw_compile_tes(const struct brw_compiler *compiler, return NULL; } - if (INTEL_DEBUG & DEBUG_TES) + if (unlikely(debug_enabled)) v.dump_instructions(); assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir, diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 7bdc92c8f61..418212dd49e 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -2837,6 +2837,7 @@ brw_compile_vs(const struct brw_compiler *compiler, struct nir_shader *nir = params->nir; const struct brw_vs_prog_key *key = params->key; struct brw_vs_prog_data *prog_data = params->prog_data; + const bool debug_enabled = INTEL_DEBUG & DEBUG_VS; prog_data->base.base.stage = MESA_SHADER_VERTEX; @@ -2935,7 +2936,7 @@ brw_compile_vs(const struct brw_compiler *compiler, prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 4); } - if (INTEL_DEBUG & DEBUG_VS) { + if (unlikely(debug_enabled)) { fprintf(stderr, "VS Output "); brw_print_vue_map(stderr, &prog_data->base.vue_map, MESA_SHADER_VERTEX); } @@ -2956,7 +2957,7 @@ brw_compile_vs(const struct brw_compiler *compiler, fs_generator g(compiler, params->log_data, mem_ctx, &prog_data->base.base, v.runtime_check_aads_emit, MESA_SHADER_VERTEX); - if (INTEL_DEBUG & DEBUG_VS) { + if (unlikely(debug_enabled)) { const char *debug_name = ralloc_asprintf(mem_ctx, "%s vertex shader %s", nir->info.label ? nir->info.label : diff --git a/src/intel/compiler/brw_vec4_gs_visitor.cpp b/src/intel/compiler/brw_vec4_gs_visitor.cpp index b9bc1834e86..c584b65a5b7 100644 --- a/src/intel/compiler/brw_vec4_gs_visitor.cpp +++ b/src/intel/compiler/brw_vec4_gs_visitor.cpp @@ -597,6 +597,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, c.key = *key; const bool is_scalar = compiler->scalar_stage[MESA_SHADER_GEOMETRY]; + const bool debug_enabled = INTEL_DEBUG & DEBUG_GS; prog_data->base.base.stage = MESA_SHADER_GEOMETRY; @@ -810,7 +811,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, /* Now that prog_data setup is done, we are ready to actually compile the * program. */ - if (INTEL_DEBUG & DEBUG_GS) { + if (unlikely(debug_enabled)) { fprintf(stderr, "GS Input "); brw_print_vue_map(stderr, &c.input_vue_map, MESA_SHADER_GEOMETRY); fprintf(stderr, "GS Output "); @@ -826,7 +827,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, fs_generator g(compiler, log_data, mem_ctx, &prog_data->base.base, false, MESA_SHADER_GEOMETRY); - if (INTEL_DEBUG & DEBUG_GS) { + if (unlikely(debug_enabled)) { const char *label = nir->info.label ? nir->info.label : "unnamed"; char *name = ralloc_asprintf(mem_ctx, "%s geometry shader %s", diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index 70cc1f359c4..607bc314101 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -368,6 +368,7 @@ brw_compile_tcs(const struct brw_compiler *compiler, const struct gen_device_info *devinfo = compiler->devinfo; struct brw_vue_prog_data *vue_prog_data = &prog_data->base; const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL]; + const bool debug_enabled = INTEL_DEBUG & DEBUG_TCS; const unsigned *assembly; vue_prog_data->base.stage = MESA_SHADER_TESS_CTRL; @@ -448,7 +449,7 @@ brw_compile_tcs(const struct brw_compiler *compiler, */ vue_prog_data->urb_read_length = 0; - if (INTEL_DEBUG & DEBUG_TCS) { + if (unlikely(debug_enabled)) { fprintf(stderr, "TCS Input "); brw_print_vue_map(stderr, &input_vue_map, MESA_SHADER_TESS_CTRL); fprintf(stderr, "TCS Output ");