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intel: Remove non-GEM support. 

This really isn't supported at this point.  GEM's been in the kernel for
a year, and the fake bufmgr never really worked.
This commit is contained in:
Eric Anholt 2009-11-18 18:15:25 +01:00
parent 667760f53c
commit 827ba44f6e
10 changed files with 43 additions and 152 deletions
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8
src/mesa/drivers/dri/i965/brw_draw_upload.c
View File

@ -243,14 +243,6 @@ static void wrap_buffers( struct brw_context *brw,
dri_bo_unreference(brw->vb.upload.bo);
brw->vb.upload.bo = dri_bo_alloc(brw->intel.bufmgr, "temporary VBO",
size, 1);
/* Set the internal VBO\ to no-backing-store. We only use them as a
* temporary within a brw_try_draw_prims while the lock is held.
*/
/* DON'T DO THIS AS IF WE HAVE TO RE-ORG MEMORY WE NEED SOMEWHERE WITH
FAKE TO PUSH THIS STUFF */
// if (!brw->intel.ttm)
// dri_bo_fake_disable_backing_store(brw->vb.upload.bo, NULL, NULL);
}
static void get_space( struct brw_context *brw,

4
src/mesa/drivers/dri/intel/intel_batchbuffer.c
View File

@ -80,7 +80,7 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch)
batch->buf = NULL;
}
if (!batch->buffer && intel->ttm == GL_TRUE)
if (!batch->buffer)
batch->buffer = malloc (intel->maxBatchSize);
batch->buf = dri_bo_alloc(intel->bufmgr, "batchbuffer",
@ -212,7 +212,7 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
batch->reserved_space = 0;
/* Emit a flush if the bufmgr doesn't do it for us. */
if (intel->always_flush_cache || !intel->ttm) {
if (intel->always_flush_cache) {
intel_batchbuffer_emit_mi_flush(batch);
used = batch->ptr - batch->map;
}

38
src/mesa/drivers/dri/intel/intel_context.c
View File

@ -176,9 +176,7 @@ intelGetString(GLcontext * ctx, GLenum name)
break;
}
(void) driGetRendererString(buffer, chipset,
(intel->ttm) ? DRIVER_DATE_GEM : DRIVER_DATE,
0);
(void) driGetRendererString(buffer, chipset, DRIVER_DATE_GEM, 0);
return (GLubyte *) buffer;
default:
@ -601,6 +599,7 @@ intelInitContext(struct intel_context *intel,
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
intelScreenPrivate *intelScreen = (intelScreenPrivate *) sPriv->private;
int fthrottle_mode;
int bo_reuse_mode;
if (!_mesa_initialize_context(&intel->ctx, mesaVis, shareCtx,
functions, (void *) intel)) {
@ -635,18 +634,14 @@ intelInitContext(struct intel_context *intel,
intel->maxBatchSize = BATCH_SZ;
intel->bufmgr = intelScreen->bufmgr;
intel->ttm = intelScreen->ttm;
if (intel->ttm) {
int bo_reuse_mode;
bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse");
switch (bo_reuse_mode) {
case DRI_CONF_BO_REUSE_DISABLED:
break;
case DRI_CONF_BO_REUSE_ALL:
intel_bufmgr_gem_enable_reuse(intel->bufmgr);
break;
}
bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse");
switch (bo_reuse_mode) {
case DRI_CONF_BO_REUSE_DISABLED:
break;
case DRI_CONF_BO_REUSE_ALL:
intel_bufmgr_gem_enable_reuse(intel->bufmgr);
break;
}
/* This doesn't yet catch all non-conformant rendering, but it's a
@ -1052,21 +1047,6 @@ intelContendedLock(struct intel_context *intel, GLuint flags)
sarea->ctxOwner = me;
}
/* If the last consumer of the texture memory wasn't us, notify the fake
* bufmgr and record the new owner. We should have the memory shared
* between contexts of a single fake bufmgr, but this will at least make
* things correct for now.
*/
if (!intel->ttm && sarea->texAge != intel->hHWContext) {
sarea->texAge = intel->hHWContext;
intel_bufmgr_fake_contended_lock_take(intel->bufmgr);
if (INTEL_DEBUG & DEBUG_BATCH)
intel_decode_context_reset();
if (INTEL_DEBUG & DEBUG_BUFMGR)
fprintf(stderr, "Lost Textures: sarea->texAge %x hw context %x\n",
sarea->ctxOwner, intel->hHWContext);
}
/* Drawable changed?
*/
if (dPriv && intel->lastStamp != dPriv->lastStamp) {

6
src/mesa/drivers/dri/intel/intel_context.h
View File

@ -181,12 +181,6 @@ struct intel_context
struct intel_region *back_region;
struct intel_region *depth_region;
/**
* This value indicates that the kernel memory manager is being used
* instead of the fake client-side memory manager.
*/
GLboolean ttm;
struct intel_batchbuffer *batch;
drm_intel_bo *first_post_swapbuffers_batch;
GLboolean no_batch_wrap;

14
src/mesa/drivers/dri/intel/intel_extensions.c
View File

@ -79,6 +79,7 @@ static const struct dri_extension card_extensions[] = {
{ "GL_ARB_half_float_pixel", NULL },
{ "GL_ARB_map_buffer_range", GL_ARB_map_buffer_range_functions },
{ "GL_ARB_multitexture", NULL },
{ "GL_ARB_pixel_buffer_object", NULL },
{ "GL_ARB_point_parameters", GL_ARB_point_parameters_functions },
{ "GL_ARB_point_sprite", NULL },
{ "GL_ARB_shader_objects", GL_ARB_shader_objects_functions },
@ -104,6 +105,8 @@ static const struct dri_extension card_extensions[] = {
{ "GL_EXT_blend_logic_op", NULL },
{ "GL_EXT_blend_subtract", NULL },
{ "GL_EXT_cull_vertex", GL_EXT_cull_vertex_functions },
{ "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions },
{ "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
{ "GL_EXT_fog_coord", GL_EXT_fog_coord_functions },
{ "GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions },
{ "GL_EXT_packed_depth_stencil", NULL },
@ -176,14 +179,6 @@ static const struct dri_extension arb_oq_extensions[] = {
{ NULL, NULL }
};
static const struct dri_extension ttm_extensions[] = {
{ "GL_ARB_pixel_buffer_object", NULL },
{ "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions },
{ "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
{ NULL, NULL }
};
static const struct dri_extension fragment_shader_extensions[] = {
{ "GL_ARB_fragment_shader", NULL },
{ NULL, NULL }
@ -202,9 +197,6 @@ intelInitExtensions(GLcontext *ctx)
*/
driInitExtensions(ctx, card_extensions, GL_FALSE);
if (intel->ttm)
driInitExtensions(ctx, ttm_extensions, GL_FALSE);
if (IS_965(intel->intelScreen->deviceID))
driInitExtensions(ctx, brw_extensions, GL_FALSE);

16
src/mesa/drivers/dri/intel/intel_mipmap_tree.c
View File

@ -224,16 +224,12 @@ int intel_miptree_pitch_align (struct intel_context *intel,
if (!mt->compressed) {
int pitch_align;
if (intel->ttm) {
/* XXX: Align pitch to multiple of 64 bytes for now to allow
* render-to-texture to work in all cases. This should probably be
* replaced at some point by some scheme to only do this when really
* necessary.
*/
pitch_align = 64;
} else {
pitch_align = 4;
}
/* XXX: Align pitch to multiple of 64 bytes for now to allow
* render-to-texture to work in all cases. This should probably be
* replaced at some point by some scheme to only do this when really
* necessary.
*/
pitch_align = 64;
if (tiling == I915_TILING_X)
pitch_align = 512;

57
src/mesa/drivers/dri/intel/intel_regions.c
View File

@ -542,55 +542,18 @@ intel_recreate_static(struct intel_context *intel,
region->buffer = NULL;
}
if (intel->ttm) {
assert(region_desc->bo_handle != -1);
region->buffer = intel_bo_gem_create_from_name(intel->bufmgr,
name,
region_desc->bo_handle);
ret = dri_bo_get_tiling(region->buffer, &region->tiling,
&region->bit_6_swizzle);
if (ret != 0) {
fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
region_desc->bo_handle, name, strerror(-ret));
intel_region_release(&region);
return NULL;
}
} else {
if (region->classic_map != NULL) {
drmUnmap(region->classic_map,
region->pitch * region->cpp * region->height);
region->classic_map = NULL;
}
ret = drmMap(intel->driFd, region_desc->handle,
region->pitch * region->cpp * region->height,
&region->classic_map);
if (ret != 0) {
fprintf(stderr, "Failed to drmMap %s buffer\n", name);
free(region);
return NULL;
}
region->buffer = intel_bo_fake_alloc_static(intel->bufmgr,
assert(region_desc->bo_handle != -1);
region->buffer = intel_bo_gem_create_from_name(intel->bufmgr,
name,
region_desc->offset,
region->pitch * region->cpp *
region->height,
region->classic_map);
region_desc->bo_handle);
/* The sarea just gives us a boolean for whether it's tiled or not,
* instead of which tiling mode it is. Guess.
*/
if (region_desc->tiled) {
if (intel->gen >= 4 && region_desc == &intelScreen->depth)
region->tiling = I915_TILING_Y;
else
region->tiling = I915_TILING_X;
} else {
region->tiling = I915_TILING_NONE;
}
region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
ret = dri_bo_get_tiling(region->buffer, &region->tiling,
&region->bit_6_swizzle);
if (ret != 0) {
fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
region_desc->bo_handle, name, strerror(-ret));
intel_region_release(&region);
return NULL;
}
assert(region->buffer != NULL);

38
src/mesa/drivers/dri/intel/intel_screen.c
View File

@ -605,7 +605,6 @@ intelFillInModes(__DRIscreenPrivate *psp,
static GLboolean
intel_init_bufmgr(intelScreenPrivate *intelScreen)
{
GLboolean gem_disable = getenv("INTEL_NO_GEM") != NULL;
int gem_kernel = 0;
GLboolean gem_supported;
struct drm_i915_getparam gp;
@ -622,43 +621,24 @@ intel_init_bufmgr(intelScreenPrivate *intelScreen)
/* If we've got a new enough DDX that's initializing GEM and giving us
* object handles for the shared buffers, use that.
*/
intelScreen->ttm = GL_FALSE;
if (intelScreen->driScrnPriv->dri2.enabled)
gem_supported = GL_TRUE;
else if (intelScreen->driScrnPriv->ddx_version.minor >= 9 &&
gem_kernel &&
intelScreen->front.bo_handle != -1)
gem_supported = GL_TRUE;
else
gem_supported = GL_FALSE;
if (!gem_disable && gem_supported) {
intelScreen->bufmgr = intel_bufmgr_gem_init(spriv->fd, BATCH_SZ);
if (intelScreen->bufmgr != NULL)
intelScreen->ttm = GL_TRUE;
else {
fprintf(stderr, "[%s:%u] Error initializing GEM.\n",
__func__, __LINE__);
return GL_FALSE;
}
intelScreen->bufmgr = intel_bufmgr_gem_init(spriv->fd, BATCH_SZ);
/* Otherwise, use the classic buffer manager. */
if (intelScreen->bufmgr == NULL) {
if (gem_disable) {
_mesa_warning(NULL, "GEM disabled. Using classic.");
} else {
_mesa_warning(NULL,
"Failed to initialize GEM. Falling back to classic.");
}
if (intelScreen->tex.size == 0) {
fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
__func__, __LINE__);
return GL_FALSE;
}
intelScreen->bufmgr =
intel_bufmgr_fake_init(spriv->fd,
intelScreen->tex.offset,
intelScreen->tex.map,
intelScreen->tex.size,
(unsigned int * volatile)
&intelScreen->sarea->last_dispatch);
fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
__func__, __LINE__);
return GL_FALSE;
}
if (intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences))

1
src/mesa/drivers/dri/intel/intel_screen.h
View File

@ -77,7 +77,6 @@ typedef struct
GLboolean no_hw;
GLboolean no_vbo;
int ttm;
dri_bufmgr *bufmgr;
GLboolean kernel_exec_fencing;

13
src/mesa/drivers/dri/intel/intel_span.c
View File

@ -613,15 +613,7 @@ intel_set_span_functions(struct intel_context *intel,
struct gl_renderbuffer *rb)
{
struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
uint32_t tiling;
/* If in GEM mode, we need to do the tile address swizzling ourselves,
* instead of the fence registers handling it.
*/
if (intel->ttm)
tiling = irb->region->tiling;
else
tiling = I915_TILING_NONE;
uint32_t tiling = irb->region->tiling;
if (intel->intelScreen->kernel_exec_fencing) {
switch (irb->texformat) {
@ -673,6 +665,9 @@ intel_set_span_functions(struct intel_context *intel,
return;
}
/* If in GEM mode, we need to do the tile address swizzling ourselves,
* instead of the fence registers handling it.
*/
switch (irb->texformat) {
case MESA_FORMAT_RGB565:
switch (tiling) {