i965/vec4: Clamp indirect tes input array reads with 0x0fffffff
Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the valid range of the offset is [0, 0FFFFFFFh]. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org
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@ -185,9 +185,19 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
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first_component /= 2;
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first_component /= 2;
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if (indirect_offset.file != BAD_FILE) {
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if (indirect_offset.file != BAD_FILE) {
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src_reg clamped_indirect_offset = src_reg(this, glsl_type::uvec4_type);
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/* Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the
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* valid range of the offset is [0, 0FFFFFFFh].
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*/
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emit_minmax(BRW_CONDITIONAL_L,
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dst_reg(clamped_indirect_offset),
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retype(indirect_offset, BRW_REGISTER_TYPE_UD),
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brw_imm_ud(0x0fffffffu));
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header = src_reg(this, glsl_type::uvec4_type);
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header = src_reg(this, glsl_type::uvec4_type);
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emit(TES_OPCODE_ADD_INDIRECT_URB_OFFSET, dst_reg(header),
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emit(TES_OPCODE_ADD_INDIRECT_URB_OFFSET, dst_reg(header),
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input_read_header, indirect_offset);
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input_read_header, clamped_indirect_offset);
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} else {
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} else {
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/* Arbitrarily only push up to 24 vec4 slots worth of data,
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/* Arbitrarily only push up to 24 vec4 slots worth of data,
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* which is 12 registers (since each holds 2 vec4 slots).
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* which is 12 registers (since each holds 2 vec4 slots).
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