freedreno/a5xx: set SP_BLEND_CONTROL properly
Signed-off-by: Rob Clark <robdclark@gmail.com>
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5b60004525
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812fd1aaa8
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@ -142,6 +142,8 @@ fd5_blend_state_create(struct pipe_context *pctx,
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so->rb_blend_cntl = A5XX_RB_BLEND_CNTL_ENABLE_BLEND(mrt_blend) |
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COND(cso->independent_blend_enable, A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND);
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so->sp_blend_cntl = A5XX_SP_BLEND_CNTL_UNK8 |
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COND(mrt_blend, A5XX_SP_BLEND_CNTL_ENABLED);
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return so;
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}
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@ -46,6 +46,7 @@ struct fd5_blend_stateobj {
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uint32_t blend_control_alpha;
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} rb_mrt[A5XX_MAX_RENDER_TARGETS];
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uint32_t rb_blend_cntl;
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uint32_t sp_blend_cntl;
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bool lrz_write;
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};
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@ -694,7 +694,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
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A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
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OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
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OUT_RING(ring, 0x00000100);
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OUT_RING(ring, blend->sp_blend_cntl);
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}
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if (dirty & FD_DIRTY_BLEND_COLOR) {
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