freedreno/a5xx: Switch to using ir3_cache for looking up our VS/FS
Saves the lock/unlock to get the variants for VS/BS/FS programs, gives us a place we could hang future linked program state, and gives us safe constlen handling that fixes a couple of our piglits. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9698>
This commit is contained in:
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ce36e60b18
commit
8120871b8d
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@ -78,10 +78,12 @@ fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
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struct fd5_emit emit = {
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struct fd5_emit emit = {
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.debug = &ctx->debug,
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.debug = &ctx->debug,
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.vtx = &ctx->vtx,
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.vtx = &ctx->vtx,
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.prog = &ctx->prog,
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.info = info,
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.info = info,
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.indirect = indirect,
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.indirect = indirect,
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.draw = draw,
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.draw = draw,
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.key = {
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.vs = ctx->prog.vs,
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.fs = ctx->prog.fs,
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.key = {
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.key = {
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.rasterflat = ctx->rasterizer->flatshade,
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.rasterflat = ctx->rasterizer->flatshade,
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.ucp_enables = ctx->rasterizer->clip_plane_enable,
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.ucp_enables = ctx->rasterizer->clip_plane_enable,
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@ -89,6 +91,7 @@ fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
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.vastc_srgb = fd5_ctx->vastc_srgb,
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.vastc_srgb = fd5_ctx->vastc_srgb,
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.fastc_srgb = fd5_ctx->fastc_srgb,
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.fastc_srgb = fd5_ctx->fastc_srgb,
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},
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},
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},
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.rasterflat = ctx->rasterizer->flatshade,
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.rasterflat = ctx->rasterizer->flatshade,
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.sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
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.sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
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.sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
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.sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
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@ -106,16 +109,20 @@ fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
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!u_trim_pipe_prim(info->mode, (unsigned*)&draw->count))
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!u_trim_pipe_prim(info->mode, (unsigned*)&draw->count))
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return false;
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return false;
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ir3_fixup_shader_state(&ctx->base, &emit.key);
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ir3_fixup_shader_state(&ctx->base, &emit.key.key);
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unsigned dirty = ctx->dirty;
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unsigned dirty = ctx->dirty;
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emit.prog = fd5_program_state(ir3_cache_lookup(ctx->shader_cache, &emit.key, &ctx->debug));
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/* bail if compile failed: */
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if (!emit.prog)
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return false;
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const struct ir3_shader_variant *vp = fd5_emit_get_vp(&emit);
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const struct ir3_shader_variant *vp = fd5_emit_get_vp(&emit);
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const struct ir3_shader_variant *fp = fd5_emit_get_fp(&emit);
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const struct ir3_shader_variant *fp = fd5_emit_get_fp(&emit);
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/* do regular pass first, since that is more likely to fail compiling: */
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/* do regular pass first: */
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if (!vp || !fp)
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return false;
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if (unlikely(ctx->stats_users > 0)) {
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if (unlikely(ctx->stats_users > 0)) {
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ctx->stats.vs_regs += ir3_shader_halfregs(vp);
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ctx->stats.vs_regs += ir3_shader_halfregs(vp);
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@ -43,12 +43,12 @@ struct fd_ringbuffer;
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struct fd5_emit {
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struct fd5_emit {
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struct pipe_debug_callback *debug;
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struct pipe_debug_callback *debug;
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const struct fd_vertex_state *vtx;
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const struct fd_vertex_state *vtx;
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const struct fd_program_stateobj *prog;
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const struct fd5_program_state *prog;
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const struct pipe_draw_info *info;
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const struct pipe_draw_info *info;
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const struct pipe_draw_indirect_info *indirect;
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const struct pipe_draw_indirect_info *indirect;
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const struct pipe_draw_start_count *draw;
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const struct pipe_draw_start_count *draw;
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bool binning_pass;
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bool binning_pass;
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struct ir3_shader_key key;
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struct ir3_cache_key key;
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enum fd_dirty_3d_state dirty;
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enum fd_dirty_3d_state dirty;
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uint32_t sprite_coord_enable; /* bitmask */
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uint32_t sprite_coord_enable; /* bitmask */
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@ -82,9 +82,10 @@ fd5_emit_get_vp(struct fd5_emit *emit)
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/* We use nonbinning VS during binning when TFB is enabled because that
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/* We use nonbinning VS during binning when TFB is enabled because that
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* is what has all the outputs that might be involved in TFB.
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* is what has all the outputs that might be involved in TFB.
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*/
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*/
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struct ir3_shader *shader = ir3_get_shader(emit->prog->vs);
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if (emit->binning_pass && !emit->prog->vs->shader->stream_output.num_outputs)
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emit->vs = ir3_shader_variant(shader, emit->key,
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emit->vs = emit->prog->bs;
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emit->binning_pass && !shader->stream_output.num_outputs, emit->debug);
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else
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emit->vs = emit->prog->vs;
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}
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}
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return emit->vs;
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return emit->vs;
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}
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}
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@ -98,9 +99,7 @@ fd5_emit_get_fp(struct fd5_emit *emit)
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static const struct ir3_shader_variant binning_fs = {};
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static const struct ir3_shader_variant binning_fs = {};
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emit->fs = &binning_fs;
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emit->fs = &binning_fs;
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} else {
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} else {
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struct ir3_shader *shader = ir3_get_shader(emit->prog->fs);
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emit->fs = emit->prog->fs;
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emit->fs = ir3_shader_variant(shader, emit->key,
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false, emit->debug);
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}
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}
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}
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}
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return emit->fs;
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return emit->fs;
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@ -374,7 +374,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
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*/
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*/
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const struct ir3_shader_variant *link_fs = s[FS].v;
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const struct ir3_shader_variant *link_fs = s[FS].v;
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if (do_streamout && emit->binning_pass)
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if (do_streamout && emit->binning_pass)
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link_fs = ir3_shader_variant(ir3_get_shader(emit->prog->fs), emit->key, false, emit->debug);
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link_fs = emit->prog->fs;
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struct ir3_shader_linkage l = {0};
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struct ir3_shader_linkage l = {0};
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ir3_link_shaders(&l, s[VS].v, link_fs, true);
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ir3_link_shaders(&l, s[VS].v, link_fs, true);
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@ -638,9 +638,46 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
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OUT_RING(ring, 0x00000000); /* VFD_CONTROL_5 */
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OUT_RING(ring, 0x00000000); /* VFD_CONTROL_5 */
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}
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}
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static struct ir3_program_state *
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fd5_program_create(void *data, struct ir3_shader_variant *bs,
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struct ir3_shader_variant *vs,
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struct ir3_shader_variant *hs,
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struct ir3_shader_variant *ds,
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struct ir3_shader_variant *gs,
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struct ir3_shader_variant *fs,
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const struct ir3_shader_key *key)
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in_dt
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{
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struct fd_context *ctx = fd_context(data);
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struct fd5_program_state *state = CALLOC_STRUCT(fd5_program_state);
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tc_assert_driver_thread(ctx->tc);
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state->bs = bs;
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state->vs = vs;
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state->fs = fs;
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return &state->base;
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}
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static void
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fd5_program_destroy(void *data, struct ir3_program_state *state)
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{
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struct fd5_program_state *so = fd5_program_state(state);
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free(so);
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}
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static const struct ir3_cache_funcs cache_funcs = {
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.create_state = fd5_program_create,
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.destroy_state = fd5_program_destroy,
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};
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void
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void
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fd5_prog_init(struct pipe_context *pctx)
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fd5_prog_init(struct pipe_context *pctx)
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{
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{
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struct fd_context *ctx = fd_context(pctx);
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ctx->shader_cache = ir3_cache_create(&cache_funcs, ctx);
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ir3_prog_init(pctx);
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ir3_prog_init(pctx);
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fd_prog_init(pctx);
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fd_prog_init(pctx);
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}
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}
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@ -30,10 +30,24 @@
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#include "pipe/p_context.h"
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#include "pipe/p_context.h"
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#include "freedreno_context.h"
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#include "freedreno_context.h"
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#include "ir3/ir3_cache.h"
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#include "ir3/ir3_shader.h"
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#include "ir3/ir3_shader.h"
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struct fd5_emit;
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struct fd5_emit;
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struct fd5_program_state {
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struct ir3_program_state base;
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struct ir3_shader_variant *bs; /* VS for when emit->binning */
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struct ir3_shader_variant *vs;
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struct ir3_shader_variant *fs; /* FS for when !emit->binning */
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};
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static inline struct fd5_program_state *
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fd5_program_state(struct ir3_program_state *state)
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{
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return (struct fd5_program_state *)state;
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}
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void fd5_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so);
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void fd5_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so);
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void fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
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void fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
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@ -35,9 +35,7 @@ glx@glx_ext_import_context@query context info,Fail
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shaders@glsl-bug-110796,Fail
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shaders@glsl-bug-110796,Fail
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shaders@glsl-kwin-blur-1,Fail
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shaders@glsl-kwin-blur-1,Fail
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shaders@glsl-kwin-blur-2,Fail
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shaders@glsl-kwin-blur-2,Fail
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shaders@glsl-uniform-interstage-limits@300 vs- 300 fs,Fail
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shaders@glsl-uniform-interstage-limits@350 vs- 350 fs,Fail
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shaders@glsl-uniform-interstage-limits@350 vs- 350 fs,Fail
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shaders@glsl-uniform-interstage-limits@400 vs- 400 fs,Fail
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shaders@point-vertex-id divisor,Crash
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shaders@point-vertex-id divisor,Crash
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shaders@point-vertex-id gl_instanceid,Crash
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shaders@point-vertex-id gl_instanceid,Crash
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shaders@point-vertex-id gl_instanceid divisor,Crash
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shaders@point-vertex-id gl_instanceid divisor,Crash
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