Revert "anv: fix dynamic state emission"
This reverts commit f348103fce
. The
change was causing performance regressions.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
This commit is contained in:
parent
69e6417e19
commit
810518fda7
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@ -3519,31 +3519,6 @@ anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline *pipeline
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return &get_vs_prog_data(pipeline)->base;
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return &get_vs_prog_data(pipeline)->base;
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}
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}
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static inline bool
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anv_cmd_buffer_needs_dynamic_state(const struct anv_cmd_buffer *cmd_buffer,
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anv_cmd_dirty_mask_t mask)
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{
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/* Only dynamic state */
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assert((mask & ANV_CMD_DIRTY_PIPELINE) == 0);
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/* If all the state is statically put into the pipeline batch, nothing to
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* do.
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*/
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if ((cmd_buffer->state.gfx.pipeline->static_state_mask & mask) == mask)
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return false;
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/* Dynamic state affected by vkCmd* commands */
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if (cmd_buffer->state.gfx.dirty & mask)
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return true;
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/* For all other states we might have part of the information in the
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* anv_graphics_pipeline::dynamic_state not emitted as part of the pipeline
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* batch so we need to reemit the packet associated with this state if the
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* pipeline changed.
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*/
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return (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) != 0;
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}
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VkResult
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VkResult
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anv_device_init_rt_shaders(struct anv_device *device);
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anv_device_init_rt_shaders(struct anv_device *device);
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@ -3965,6 +3965,11 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) {
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) {
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anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->base.batch);
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anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->base.batch);
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/* Remove from dynamic state emission all of stuff that is baked into
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* the pipeline.
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*/
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cmd_buffer->state.gfx.dirty &= ~pipeline->static_state_mask;
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/* If the pipeline changed, we may need to re-allocate push constant
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/* If the pipeline changed, we may need to re-allocate push constant
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* space in the URB.
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* space in the URB.
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*/
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*/
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@ -4038,23 +4043,23 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
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cmd_buffer_emit_clip(cmd_buffer);
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cmd_buffer_emit_clip(cmd_buffer);
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE) {
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ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE))
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE | ANV_CMD_DIRTY_XFB_ENABLE))
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cmd_buffer_emit_streamout(cmd_buffer);
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cmd_buffer_emit_streamout(cmd_buffer);
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}
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_SCISSOR |
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ANV_CMD_DIRTY_DYNAMIC_SCISSOR |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_VIEWPORT |
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ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)) {
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ANV_CMD_DIRTY_PIPELINE)) {
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cmd_buffer_emit_viewport(cmd_buffer);
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cmd_buffer_emit_viewport(cmd_buffer);
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cmd_buffer_emit_depth_viewport(cmd_buffer,
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cmd_buffer_emit_depth_viewport(cmd_buffer,
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pipeline->depth_clamp_enable);
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pipeline->depth_clamp_enable);
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}
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}
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_SCISSOR |
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ANV_CMD_DIRTY_DYNAMIC_SCISSOR |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_VIEWPORT))
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ANV_CMD_DIRTY_DYNAMIC_VIEWPORT))
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cmd_buffer_emit_scissor(cmd_buffer);
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cmd_buffer_emit_scissor(cmd_buffer);
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genX(cmd_buffer_flush_dynamic_state)(cmd_buffer);
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genX(cmd_buffer_flush_dynamic_state)(cmd_buffer);
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@ -110,8 +110,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
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struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
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struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
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struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY) {
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
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uint32_t topology;
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uint32_t topology;
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if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
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if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
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topology = pipeline->topology;
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topology = pipeline->topology;
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@ -121,22 +120,24 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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cmd_buffer->state.gfx.primitive_topology = topology;
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cmd_buffer->state.gfx.primitive_topology = topology;
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}
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}
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
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ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS |
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ANV_CMD_DIRTY_DYNAMIC_CULL_MODE |
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ANV_CMD_DIRTY_DYNAMIC_CULL_MODE |
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ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE |
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ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
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/* Take dynamic primitive topology in to account with
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/* Take dynamic primitive topology in to account with
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* 3DSTATE_SF::MultisampleRasterizationMode
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* 3DSTATE_SF::MultisampleRasterizationMode
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*/
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*/
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uint32_t ms_rast_mode = 0;
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uint32_t ms_rast_mode = 0;
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.pipeline->dynamic_states &
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY) {
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VkPrimitiveTopology primitive_topology = d->primitive_topology;
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VkPrimitiveTopology primitive_topology =
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cmd_buffer->state.gfx.dynamic.primitive_topology;
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VkPolygonMode dynamic_raster_mode =
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VkPolygonMode dynamic_raster_mode =
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genX(raster_polygon_mode)(cmd_buffer->state.gfx.pipeline,
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genX(raster_polygon_mode)(cmd_buffer->state.gfx.pipeline,
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primitive_topology);
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primitive_topology);
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@ -165,9 +166,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gfx7.sf);
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anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gfx7.sf);
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}
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}
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
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ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
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struct anv_state cc_state =
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struct anv_state cc_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
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GENX(COLOR_CALC_STATE_length) * 4,
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GENX(COLOR_CALC_STATE_length) * 4,
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@ -187,8 +187,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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}
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}
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}
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}
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE) {
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ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)) {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) {
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ls.LineStipplePattern = d->line_stipple.pattern;
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ls.LineStipplePattern = d->line_stipple.pattern;
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ls.LineStippleInverseRepeatCount =
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ls.LineStippleInverseRepeatCount =
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@ -197,15 +196,15 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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}
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}
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}
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}
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP)) {
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP)) {
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uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
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uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
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struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
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struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
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@ -246,9 +245,9 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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}
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}
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if (cmd_buffer->state.gfx.gfx7.index_buffer &&
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if (cmd_buffer->state.gfx.gfx7.index_buffer &&
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anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_INDEX_BUFFER |
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ANV_CMD_DIRTY_INDEX_BUFFER |
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE)) {
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE)) {
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struct anv_buffer *buffer = cmd_buffer->state.gfx.gfx7.index_buffer;
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struct anv_buffer *buffer = cmd_buffer->state.gfx.gfx7.index_buffer;
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uint32_t offset = cmd_buffer->state.gfx.gfx7.index_offset;
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uint32_t offset = cmd_buffer->state.gfx.gfx7.index_offset;
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@ -278,9 +277,9 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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* threads or if we have dirty dynamic primitive topology state and
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* threads or if we have dirty dynamic primitive topology state and
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* need to toggle 3DSTATE_WM::MultisampleRasterizationMode dynamically.
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* need to toggle 3DSTATE_WM::MultisampleRasterizationMode dynamically.
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*/
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*/
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
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ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
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VkPolygonMode dynamic_raster_mode;
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VkPolygonMode dynamic_raster_mode;
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VkPrimitiveTopology primitive_topology = d->primitive_topology;
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VkPrimitiveTopology primitive_topology = d->primitive_topology;
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dynamic_raster_mode =
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dynamic_raster_mode =
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@ -302,18 +301,17 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx7.wm);
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anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx7.wm);
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}
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}
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS) {
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ANV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)) {
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genX(emit_multisample)(&cmd_buffer->batch,
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genX(emit_multisample)(&cmd_buffer->batch,
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pipeline->rasterization_samples,
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pipeline->rasterization_samples,
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d->sample_locations.locations);
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d->sample_locations.locations);
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}
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}
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
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ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
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ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
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ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
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const uint8_t color_writes = cmd_buffer->state.gfx.dynamic.color_writes;
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const uint8_t color_writes = d->color_writes;
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/* Blend states of each RT */
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uint32_t blend_dws[GENX(BLEND_STATE_length) +
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uint32_t blend_dws[GENX(BLEND_STATE_length) +
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MAX_RTS * GENX(BLEND_STATE_ENTRY_length)];
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MAX_RTS * GENX(BLEND_STATE_ENTRY_length)];
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uint32_t *dws = blend_dws;
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uint32_t *dws = blend_dws;
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@ -323,14 +323,11 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
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struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
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#if GFX_VER >= 11
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#if GFX_VER >= 11
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_SHADING_RATE)
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ANV_CMD_DIRTY_DYNAMIC_SHADING_RATE)) {
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genX(emit_shading_rate)(&cmd_buffer->batch, pipeline, d);
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genX(emit_shading_rate)(&cmd_buffer->batch, pipeline, d);
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}
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#endif /* GFX_VER >= 11 */
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#endif /* GFX_VER >= 11 */
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY) {
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
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uint32_t topology;
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uint32_t topology;
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if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
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if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
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topology = pipeline->topology;
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topology = pipeline->topology;
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@ -344,8 +341,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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}
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}
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}
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}
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
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ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
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uint32_t sf_dw[GENX(3DSTATE_SF_length)];
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uint32_t sf_dw[GENX(3DSTATE_SF_length)];
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struct GENX(3DSTATE_SF) sf = {
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struct GENX(3DSTATE_SF) sf = {
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GENX(3DSTATE_SF_header),
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GENX(3DSTATE_SF_header),
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@ -363,12 +360,12 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gfx8.sf);
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anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gfx8.sf);
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}
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}
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if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS |
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ANV_CMD_DIRTY_DYNAMIC_CULL_MODE |
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ANV_CMD_DIRTY_DYNAMIC_CULL_MODE |
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ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE |
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ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
|
ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
|
||||||
/* Take dynamic primitive topology in to account with
|
/* Take dynamic primitive topology in to account with
|
||||||
* 3DSTATE_RASTER::APIMode
|
* 3DSTATE_RASTER::APIMode
|
||||||
* 3DSTATE_RASTER::DXMultisampleRasterizationEnable
|
* 3DSTATE_RASTER::DXMultisampleRasterizationEnable
|
||||||
|
@ -378,8 +375,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
|
||||||
bool msaa_raster_enable = false;
|
bool msaa_raster_enable = false;
|
||||||
bool aa_enable = 0;
|
bool aa_enable = 0;
|
||||||
|
|
||||||
if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
|
if (cmd_buffer->state.gfx.pipeline->dynamic_states &
|
||||||
ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
|
ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY) {
|
||||||
VkPrimitiveTopology primitive_topology =
|
VkPrimitiveTopology primitive_topology =
|
||||||
cmd_buffer->state.gfx.dynamic.primitive_topology;
|
cmd_buffer->state.gfx.dynamic.primitive_topology;
|
||||||
|
|
||||||
|
@ -422,9 +419,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
|
||||||
* using a big old #if switch here.
|
* using a big old #if switch here.
|
||||||
*/
|
*/
|
||||||
#if GFX_VER == 8
|
#if GFX_VER == 8
|
||||||
if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
|
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
|
||||||
ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
|
|
||||||
struct anv_state cc_state =
|
struct anv_state cc_state =
|
||||||
anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
|
anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
|
||||||
GENX(COLOR_CALC_STATE_length) * 4,
|
GENX(COLOR_CALC_STATE_length) * 4,
|
||||||
|
@ -445,15 +441,15 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
|
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
||||||
ANV_CMD_DIRTY_RENDER_TARGETS |
|
ANV_CMD_DIRTY_RENDER_TARGETS |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
|
ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
|
ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
|
ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP)) {
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP)) {
|
||||||
uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
|
uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
|
||||||
|
|
||||||
struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
|
struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
|
||||||
|
@ -492,8 +488,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
|
||||||
want_depth_pma_fix(cmd_buffer));
|
want_depth_pma_fix(cmd_buffer));
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
|
if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
|
||||||
ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)) {
|
|
||||||
struct anv_state cc_state =
|
struct anv_state cc_state =
|
||||||
anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
|
anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
|
||||||
GENX(COLOR_CALC_STATE_length) * 4,
|
GENX(COLOR_CALC_STATE_length) * 4,
|
||||||
|
@ -512,16 +507,16 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
|
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
||||||
ANV_CMD_DIRTY_RENDER_TARGETS |
|
ANV_CMD_DIRTY_RENDER_TARGETS |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
|
ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
|
ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
|
ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP)) {
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP)) {
|
||||||
uint32_t dwords[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
|
uint32_t dwords[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
|
||||||
struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
|
struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
|
||||||
GENX(3DSTATE_WM_DEPTH_STENCIL_header),
|
GENX(3DSTATE_WM_DEPTH_STENCIL_header),
|
||||||
|
@ -564,9 +559,9 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if GFX_VER >= 12
|
#if GFX_VER >= 12
|
||||||
if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
|
if(cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS |
|
ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE)) {
|
ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE)) {
|
||||||
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BOUNDS), db) {
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BOUNDS), db) {
|
||||||
db.DepthBoundsTestEnable = d->depth_bounds_test_enable;
|
db.DepthBoundsTestEnable = d->depth_bounds_test_enable;
|
||||||
db.DepthBoundsTestMinValue = d->depth_bounds.min;
|
db.DepthBoundsTestMinValue = d->depth_bounds.min;
|
||||||
|
@ -575,8 +570,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
|
if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE) {
|
||||||
ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)) {
|
|
||||||
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) {
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) {
|
||||||
ls.LineStipplePattern = d->line_stipple.pattern;
|
ls.LineStipplePattern = d->line_stipple.pattern;
|
||||||
ls.LineStippleInverseRepeatCount =
|
ls.LineStippleInverseRepeatCount =
|
||||||
|
@ -585,9 +579,9 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
|
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
||||||
ANV_CMD_DIRTY_INDEX_BUFFER |
|
ANV_CMD_DIRTY_INDEX_BUFFER |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE)) {
|
ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE)) {
|
||||||
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
|
||||||
#if GFX_VERx10 >= 125
|
#if GFX_VERx10 >= 125
|
||||||
vf.GeometryDistributionEnable = true;
|
vf.GeometryDistributionEnable = true;
|
||||||
|
@ -598,8 +592,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
|
||||||
}
|
}
|
||||||
|
|
||||||
#if GFX_VERx10 >= 125
|
#if GFX_VERx10 >= 125
|
||||||
if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
|
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE)) {
|
ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE)) {
|
||||||
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VFG), vfg) {
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VFG), vfg) {
|
||||||
/* If 3DSTATE_TE: TE Enable == 1 then RR_STRICT else RR_FREE*/
|
/* If 3DSTATE_TE: TE Enable == 1 then RR_STRICT else RR_FREE*/
|
||||||
vfg.DistributionMode =
|
vfg.DistributionMode =
|
||||||
|
@ -628,16 +622,15 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
|
if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS) {
|
||||||
ANV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)) {
|
|
||||||
genX(emit_sample_pattern)(&cmd_buffer->batch,
|
genX(emit_sample_pattern)(&cmd_buffer->batch,
|
||||||
pipeline->rasterization_samples,
|
pipeline->rasterization_samples,
|
||||||
d->sample_locations.locations);
|
d->sample_locations.locations);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (anv_cmd_buffer_needs_dynamic_state(cmd_buffer,
|
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
|
ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
|
||||||
ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
|
ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
|
||||||
const uint8_t color_writes = d->color_writes;
|
const uint8_t color_writes = d->color_writes;
|
||||||
/* 3DSTATE_WM in the hope we can avoid spawning fragment shaders
|
/* 3DSTATE_WM in the hope we can avoid spawning fragment shaders
|
||||||
* threads.
|
* threads.
|
||||||
|
|
Loading…
Reference in New Issue