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iris: Stop calling I915_GEM_SET_CACHING on discrete GPUs 

On integrated GPUs without LLC, we enable snooping when someone requests
coherency for a buffer.  (With LLC, it's already coherent.)

For discrete GPUs...if someone requests coherency, we allocate the
buffer in SMEM and resort to WC maps rather than WB maps with CPU
caches enabled.  There's no snooping to enable, and calling this ioctl
is nonsensical, and may fail.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11644>
This commit is contained in:
Kenneth Graunke 2021-06-28 11:31:50 -07:00 committed by Marge Bot
parent 5c55f59b13
commit 803a2a9b3d
1 changed files with 5 additions and 1 deletions
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6
src/gallium/drivers/iris/iris_bufmgr.c
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@ -664,7 +664,11 @@ iris_bo_alloc(struct iris_bufmgr *bufmgr,
assert(bo->map == NULL || bo->mmap_mode == mmap_mode);
bo->mmap_mode = mmap_mode;
if ((flags & BO_ALLOC_COHERENT) && !bo->cache_coherent) {
/* On integrated GPUs, enable snooping to ensure coherency if needed.
* For discrete, we instead use SMEM and avoid WB maps for coherency.
*/
if (bufmgr->vram.size == 0 &&
(flags & BO_ALLOC_COHERENT) && !bo->cache_coherent) {
struct drm_i915_gem_caching arg = {
.handle = bo->gem_handle,
.caching = 1,