radeon/llvm: Sort tgsi opcode action initialization
This was done in order to identify and remove duplicate entries.
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@ -1068,73 +1068,26 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
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lp_set_default_actions(bld_base);
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bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
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bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
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bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
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bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
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bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
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bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
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bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
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bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
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bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
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bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
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bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
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bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
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bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
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bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
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bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
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bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
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bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
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bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
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bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
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bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
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bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx";
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bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
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bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
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bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
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bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
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bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
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bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
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bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
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bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
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bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
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bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max.";
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bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
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bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
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bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
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bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
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bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
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bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
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bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly;
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bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";
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bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_readonly;
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bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "fabs";
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bld_base->op_actions[TGSI_OPCODE_ARL].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_ARL].intr_name = "llvm.AMDGPU.arl";
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bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
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bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
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bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
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bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
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bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly;
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bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";
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bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
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bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
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bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
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bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_readonly;
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bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
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bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx";
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bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
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bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_DIV].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_DIV].intr_name = "llvm.AMDGPU.div";
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bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
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@ -1146,7 +1099,22 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
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bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "floor";
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bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction.";
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bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
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bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
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bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
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bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
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bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
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bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
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bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
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bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
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bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
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bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
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bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
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bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
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bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
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bld_base->op_actions[TGSI_OPCODE_KIL].emit = kil_emit;
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bld_base->op_actions[TGSI_OPCODE_KIL].intr_name = "llvm.AMDGPU.kill";
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bld_base->op_actions[TGSI_OPCODE_KILP].emit = lp_build_tgsi_intrinsic;
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@ -1155,40 +1123,63 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
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bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
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bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
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bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
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bld_base->op_actions[TGSI_OPCODE_MAD].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_MAD].intr_name = "llvm.AMDIL.mad.";
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bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max.";
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bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
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bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
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bld_base->op_actions[TGSI_OPCODE_MUL].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_MUL].intr_name = "llvm.AMDGPU.mul";
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bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
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bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
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bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_readonly;
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bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
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bld_base->op_actions[TGSI_OPCODE_RCP].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_RCP].intr_name = "llvm.AMDGPU.rcp";
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bld_base->op_actions[TGSI_OPCODE_SSG].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_SSG].intr_name = "llvm.AMDGPU.ssg";
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bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
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bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;
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bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp;
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bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
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bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp;
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bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp;
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bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp;
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bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp;
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bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_readonly;
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bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
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bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
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bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex";
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bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb";
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bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = txd_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd";
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bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
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bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl";
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bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex";
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bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
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bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc";
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bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
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bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
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bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
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bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
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bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
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bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
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bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
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bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
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bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
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bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
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bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
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bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
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bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
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bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
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bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
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