amd/addrlib: update to latest version
This uses C++11 initializer lists. I just overwrote all Mesa files with internal addrlib and discarded hunks that we should probably keep, but I might have missed something. The code depending on ADDR_AM_BUILD is removed. We can add it back next time if needed. Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
parent
3bfcd31e98
commit
7f33e94e43
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@ -2,8 +2,7 @@ COMMON_HEADER_FILES = \
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common/gfx9d.h \
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common/sid.h \
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common/amd_family.h \
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common/amd_kernel_code_t.h \
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common/amdgpu_id.h
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common/amd_kernel_code_t.h
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ADDRLIB_FILES = \
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addrlib/addrinterface.cpp \
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@ -25,11 +24,8 @@ ADDRLIB_FILES = \
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addrlib/gfx9/coord.h \
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addrlib/gfx9/gfx9addrlib.cpp \
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addrlib/gfx9/gfx9addrlib.h \
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addrlib/gfx9/rbmap.cpp \
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addrlib/gfx9/rbmap.h \
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addrlib/inc/chip/gfx9/gfx9_gb_reg.h \
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addrlib/inc/chip/r800/si_gb_reg.h \
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addrlib/inc/lnx_common_defs.h \
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addrlib/r800/chip/si_ci_vi_merged_enum.h \
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addrlib/r800/ciaddrlib.cpp \
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addrlib/r800/ciaddrlib.h \
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@ -534,11 +534,11 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
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if (pLib != NULL)
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{
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returnCode = pLib->ComputeDccInfo(pIn, pOut);
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returnCode = pLib->ComputeDccInfo(pIn, pOut);
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}
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else
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{
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returnCode = ADDR_ERROR;
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returnCode = ADDR_ERROR;
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}
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return returnCode;
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@ -528,7 +528,7 @@ typedef union _ADDR_SURFACE_FLAGS
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UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode
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UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface
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/// to make sure they share same tile config parameters
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UINT_32 reserved : 3; ///< Reserved bits
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UINT_32 reserved : 2; ///< Reserved bits
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};
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UINT_32 value;
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@ -714,12 +714,6 @@ typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
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};
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UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
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};
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#if ADDR_AM_BUILD // These two fields are not valid in SW blt since no HTILE access
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UINT_32 addr5Swizzle; ///< ADDR5_SWIZZLE_MASK of DB_DEPTH_INFO
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BOOL_32 is32ByteTile; ///< Caller must have access to HTILE buffer and know if
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/// this tile is compressed to 32B
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#endif
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} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
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/**
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@ -857,8 +851,11 @@ typedef union _ADDR_HTILE_FLAGS
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{
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struct
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{
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UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
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UINT_32 reserved :31; ///< Reserved bits
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UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
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UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile
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/// size to 256xBankxPipe when computing tc-compatible
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/// htile info.
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UINT_32 reserved : 30; ///< Reserved bits
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};
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UINT_32 value;
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@ -915,6 +912,9 @@ typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT
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UINT_64 sliceSize; ///< Slice size, in bytes.
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BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved
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/// Compute engine clear can't be used if htile is interleaved
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BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in
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/// next mip level, it also indicates if memory set based
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/// fast clear can be used for current mip level.
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} ADDR_COMPUTE_HTILE_INFO_OUTPUT;
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/**
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@ -2188,7 +2188,6 @@ ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex(
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/**
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****************************************************************************************************
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* ADDR_PRT_INFO_INPUT
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@ -2233,6 +2232,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
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const ADDR_PRT_INFO_INPUT* pIn,
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ADDR_PRT_INFO_OUTPUT* pOut);
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// DCC key functions
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////////////////////////////////////////////////////////////////////////////////////////////////////
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@ -2293,6 +2294,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
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const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
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ADDR_COMPUTE_DCCINFO_OUTPUT* pOut);
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/**
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****************************************************************************************************
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* ADDR_GET_MAX_ALIGNMENTS_OUTPUT
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@ -2693,10 +2696,8 @@ typedef struct _ADDR2_META_MIP_INFO
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struct
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{
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UINT_32 offset; ///< metadata offset within one slice,
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/// the thickness of a slice is meta block depth.
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UINT_32 sliceSize; ///< metadata size within one slice,
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/// the thickness of a slice is meta block depth.
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UINT_32 offset;
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UINT_32 sliceSize;
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};
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};
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} ADDR2_META_MIP_INFO;
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@ -2720,9 +2721,7 @@ typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT
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UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
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UINT_32 numSlices; ///< Number of slices of depth surface (of mip0)
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UINT_32 numMipLevels; ///< Total mipmap levels of color surface
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UINT_32 firstMipIdInTail; ///< id of the first mip in tail,
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/// if no mip is in tail, it should be set to
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/// number of mip levels
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UINT_32 firstMipIdInTail;
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} ADDR2_COMPUTE_HTILE_INFO_INPUT;
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/**
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@ -3308,8 +3307,7 @@ typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT
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UINT_32 numMipLevels; ///< Total mipmap levels of color surface
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UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels
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///< useful in meta linear case
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UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,
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/// it should be number of mip levels
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UINT_32 firstMipIdInTail;
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} ADDR2_COMPUTE_DCCINFO_INPUT;
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/**
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@ -3339,8 +3337,13 @@ typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT
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UINT_32 metaBlkHeight; ///< DCC meta block height
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UINT_32 metaBlkDepth; ///< DCC meta block depth
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UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared
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UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
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UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
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union
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{
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UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared
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UINT_32 dccRamSliceSize;
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};
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ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information
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} ADDR2_COMPUTE_DCCINFO_OUTPUT;
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@ -3571,7 +3574,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern(
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* ADDR2_BLOCK_SET
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*
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* @brief
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* Bit field that define block type
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* Bit field that defines block type
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****************************************************************************************************
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*/
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typedef union _ADDR2_BLOCK_SET
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@ -3589,6 +3592,28 @@ typedef union _ADDR2_BLOCK_SET
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UINT_32 value;
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} ADDR2_BLOCK_SET;
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/**
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****************************************************************************************************
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* ADDR2_SWTYPE_SET
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*
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* @brief
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* Bit field that defines swizzle type
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****************************************************************************************************
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*/
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typedef union _ADDR2_SWTYPE_SET
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{
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struct
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{
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UINT_32 sw_Z : 1; // SW_*_Z_*
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UINT_32 sw_S : 1; // SW_*_S_*
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UINT_32 sw_D : 1; // SW_*_D_*
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UINT_32 sw_R : 1; // SW_*_R_*
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UINT_32 reserved : 28;
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};
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UINT_32 value;
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} ADDR2_SWTYPE_SET;
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/**
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****************************************************************************************************
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* ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
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@ -3607,6 +3632,7 @@ typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
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AddrResrouceLocation resourceLoction; ///< Surface heap choice
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ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting
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///< such as linear for DXTn, tiled for YUV
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ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted
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BOOL_32 noXor; ///< Do not use xor mode for this resource
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UINT_32 bpp; ///< bits per pixel
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UINT_32 width; ///< Width (of mip0), in pixels
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*/
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typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
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{
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UINT_32 size; ///< Size of this structure in bytes
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UINT_32 size; ///< Size of this structure in bytes
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AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used
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AddrResourceType resourceType; ///< Suggested resource type to program HW
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ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination
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BOOL_32 canXor; ///< If client can use xor on a valid macro block type
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AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used
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AddrResourceType resourceType; ///< Suggested resource type to program HW
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ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination
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BOOL_32 canXor; ///< If client can use xor on a valid macro block
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/// type
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ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination
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ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination
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} ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT;
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/**
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@ -0,0 +1,129 @@
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/*
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* Copyright © 2017 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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#ifndef _AMDGPU_ASIC_ADDR_H
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#define _AMDGPU_ASIC_ADDR_H
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#define ATI_VENDOR_ID 0x1002
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#define AMD_VENDOR_ID 0x1022
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// AMDGPU_VENDOR_IS_AMD(vendorId)
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#define AMDGPU_VENDOR_IS_AMD(v) ((v == ATI_VENDOR_ID) || (v == AMD_VENDOR_ID))
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#define FAMILY_UNKNOWN 0x00
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#define FAMILY_TN 0x69
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#define FAMILY_SI 0x6E
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#define FAMILY_CI 0x78
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#define FAMILY_KV 0x7D
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#define FAMILY_VI 0x82
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#define FAMILY_POLARIS 0x82
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#define FAMILY_CZ 0x87
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#define FAMILY_AI 0x8D
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#define FAMILY_RV 0x8E
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// AMDGPU_FAMILY_IS(familyId, familyName)
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#define FAMILY_IS(f, fn) (f == FAMILY_##fn)
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#define FAMILY_IS_TN(f) FAMILY_IS(f, TN)
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#define FAMILY_IS_SI(f) FAMILY_IS(f, SI)
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#define FAMILY_IS_CI(f) FAMILY_IS(f, CI)
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#define FAMILY_IS_KV(f) FAMILY_IS(f, KV)
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#define FAMILY_IS_VI(f) FAMILY_IS(f, VI)
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#define FAMILY_IS_POLARIS(f) FAMILY_IS(f, POLARIS)
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#define FAMILY_IS_CZ(f) FAMILY_IS(f, CZ)
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#define FAMILY_IS_AI(f) FAMILY_IS(f, AI)
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#define FAMILY_IS_RV(f) FAMILY_IS(f, RV)
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#define AMDGPU_UNKNOWN 0xFF
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#define AMDGPU_TAHITI_RANGE 0x05, 0x14
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#define AMDGPU_PITCAIRN_RANGE 0x15, 0x28
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#define AMDGPU_CAPEVERDE_RANGE 0x29, 0x3C
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#define AMDGPU_OLAND_RANGE 0x3C, 0x46
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#define AMDGPU_HAINAN_RANGE 0x46, 0xFF
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#define AMDGPU_BONAIRE_RANGE 0x14, 0x28
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#define AMDGPU_HAWAII_RANGE 0x28, 0x3C
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#define AMDGPU_SPECTRE_RANGE 0x01, 0x41
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#define AMDGPU_SPOOKY_RANGE 0x41, 0x81
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#define AMDGPU_KALINDI_RANGE 0x81, 0xA1
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#define AMDGPU_GODAVARI_RANGE 0xA1, 0xFF
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#define AMDGPU_ICELAND_RANGE 0x01, 0x14
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#define AMDGPU_TONGA_RANGE 0x14, 0x28
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#define AMDGPU_FIJI_RANGE 0x3C, 0x50
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#define AMDGPU_POLARIS10_RANGE 0x50, 0x5A
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#define AMDGPU_POLARIS11_RANGE 0x5A, 0x64
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#define AMDGPU_POLARIS12_RANGE 0x64, 0x6E
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#define AMDGPU_CARRIZO_RANGE 0x01, 0x21
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#define AMDGPU_BRISTOL_RANGE 0x10, 0x21
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#define AMDGPU_STONEY_RANGE 0x61, 0xFF
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#define AMDGPU_VEGA10_RANGE 0x01, 0x14
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#define AMDGPU_RAVEN_RANGE 0x01, 0x81
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#define AMDGPU_EXPAND_FIX(x) x
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#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
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#define AMDGPU_IN_RANGE(val, ...) AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
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// ASICREV_IS(eRevisionId, revisionName)
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#define ASICREV_IS(r, rn) AMDGPU_IN_RANGE(r, AMDGPU_##rn##_RANGE)
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#define ASICREV_IS_TAHITI_P(r) ASICREV_IS(r, TAHITI)
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#define ASICREV_IS_PITCAIRN_PM(r) ASICREV_IS(r, PITCAIRN)
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#define ASICREV_IS_CAPEVERDE_M(r) ASICREV_IS(r, CAPEVERDE)
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#define ASICREV_IS_OLAND_M(r) ASICREV_IS(r, OLAND)
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#define ASICREV_IS_HAINAN_V(r) ASICREV_IS(r, HAINAN)
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#define ASICREV_IS_BONAIRE_M(r) ASICREV_IS(r, BONAIRE)
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#define ASICREV_IS_HAWAII_P(r) ASICREV_IS(r, HAWAII)
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#define ASICREV_IS_SPECTRE(r) ASICREV_IS(r, SPECTRE)
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#define ASICREV_IS_SPOOKY(r) ASICREV_IS(r, SPOOKY)
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#define ASICREV_IS_KALINDI(r) ASICREV_IS(r, KALINDI)
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#define ASICREV_IS_KALINDI_GODAVARI(r) ASICREV_IS(r, GODAVARI)
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#define ASICREV_IS_ICELAND_M(r) ASICREV_IS(r, ICELAND)
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#define ASICREV_IS_TONGA_P(r) ASICREV_IS(r, TONGA)
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#define ASICREV_IS_FIJI_P(r) ASICREV_IS(r, FIJI)
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#define ASICREV_IS_POLARIS10_P(r) ASICREV_IS(r, POLARIS10)
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#define ASICREV_IS_POLARIS11_M(r) ASICREV_IS(r, POLARIS11)
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#define ASICREV_IS_POLARIS12_V(r) ASICREV_IS(r, POLARIS12)
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#define ASICREV_IS_CARRIZO(r) ASICREV_IS(r, CARRIZO)
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#define ASICREV_IS_CARRIZO_BRISTOL(r) ASICREV_IS(r, BRISTOL)
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#define ASICREV_IS_STONEY(r) ASICREV_IS(r, STONEY)
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#define ASICREV_IS_VEGA10_M(r) ASICREV_IS(r, VEGA10)
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#define ASICREV_IS_VEGA10_P(r) ASICREV_IS(r, VEGA10)
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#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
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#endif // _AMDGPU_ASIC_ADDR_H
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@ -36,15 +36,9 @@
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#include "addrinterface.h"
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// ADDR_LNX_KERNEL_BUILD is for internal build
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// Moved from addrinterface.h so __KERNEL__ is not needed any more
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#if ADDR_LNX_KERNEL_BUILD // || (defined(__GNUC__) && defined(__KERNEL__))
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#include "lnx_common_defs.h" // ported from cmmqs
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#elif !defined(__APPLE__) || defined(HAVE_TSERVER)
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#include <assert.h>
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#include <stdlib.h>
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#include <string.h>
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#endif
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#if BRAHMA_BUILD && !defined(DEBUG)
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#ifdef NDEBUG
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@ -171,6 +165,8 @@
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#endif // DEBUG
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////////////////////////////////////////////////////////////////////////////////////////////////////
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#define ADDR_C_ASSERT(__e) typedef char __ADDR_C_ASSERT__[(__e) ? 1 : -1]
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namespace Addr
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{
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@ -1271,6 +1271,9 @@ VOID ElemLib::RestoreSurfaceInfo(
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UINT_32 height;
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UINT_32 bpp;
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BOOL_32 bBCnFormat = FALSE;
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(void)bBCnFormat;
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|
||||
ADDR_ASSERT(pBpp != NULL);
|
||||
ADDR_ASSERT(pWidth != NULL && pHeight != NULL);
|
||||
|
||||
|
@ -1289,22 +1292,17 @@ VOID ElemLib::RestoreSurfaceInfo(
|
|||
break;
|
||||
case ADDR_PACKED_GBGR:
|
||||
case ADDR_PACKED_BGRG:
|
||||
if (m_pAddrLib->GetChipFamily() >= ADDR_CHIP_FAMILY_AI)
|
||||
{
|
||||
originalBits = bpp / expandX;
|
||||
}
|
||||
else
|
||||
{
|
||||
originalBits = bpp; // 32-bit packed ==> 2 32-bit result
|
||||
}
|
||||
originalBits = bpp; // 32-bit packed ==> 2 32-bit result
|
||||
break;
|
||||
case ADDR_PACKED_BC1: // Fall through
|
||||
case ADDR_PACKED_BC4:
|
||||
originalBits = 64;
|
||||
bBCnFormat = TRUE;
|
||||
break;
|
||||
case ADDR_PACKED_BC2: // Fall through
|
||||
case ADDR_PACKED_BC3: // Fall through
|
||||
case ADDR_PACKED_BC5:
|
||||
bBCnFormat = TRUE;
|
||||
// fall through
|
||||
case ADDR_PACKED_ASTC:
|
||||
case ADDR_PACKED_ETC2_128BPP:
|
||||
|
@ -1394,27 +1392,11 @@ UINT_32 ElemLib::GetBitsPerPixel(
|
|||
break;
|
||||
case ADDR_FMT_GB_GR: // treat as FMT_8_8
|
||||
elemMode = ADDR_PACKED_GBGR;
|
||||
if (m_pAddrLib->GetChipFamily() >= ADDR_CHIP_FAMILY_AI)
|
||||
{
|
||||
bpp = 32;
|
||||
expandX = 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
bpp = 16;
|
||||
}
|
||||
bpp = 16;
|
||||
break;
|
||||
case ADDR_FMT_BG_RG: // treat as FMT_8_8
|
||||
elemMode = ADDR_PACKED_BGRG;
|
||||
if (m_pAddrLib->GetChipFamily() >= ADDR_CHIP_FAMILY_AI)
|
||||
{
|
||||
bpp = 32;
|
||||
expandX = 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
bpp = 16;
|
||||
}
|
||||
bpp = 16;
|
||||
break;
|
||||
case ADDR_FMT_8_8_8_8:
|
||||
case ADDR_FMT_2_10_10_10:
|
||||
|
|
|
@ -218,7 +218,16 @@ ADDR_E_RETURNCODE Lib::Create(
|
|||
}
|
||||
break;
|
||||
case CIASICIDGFXENGINE_ARCTICISLAND:
|
||||
pLib = Gfx9HwlInit(&client);
|
||||
switch (pCreateIn->chipFamily)
|
||||
{
|
||||
case FAMILY_AI:
|
||||
case FAMILY_RV:
|
||||
pLib = Gfx9HwlInit(&client);
|
||||
break;
|
||||
default:
|
||||
ADDR_ASSERT_ALWAYS();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
ADDR_ASSERT_ALWAYS();
|
||||
|
|
|
@ -38,11 +38,7 @@
|
|||
#include "addrobject.h"
|
||||
#include "addrelemlib.h"
|
||||
|
||||
#if BRAHMA_BUILD
|
||||
#include "amdgpu_id.h"
|
||||
#else
|
||||
#include "atiid.h"
|
||||
#endif
|
||||
#include "amdgpu_asic_addr.h"
|
||||
|
||||
#ifndef CIASICIDGFXENGINE_R600
|
||||
#define CIASICIDGFXENGINE_R600 0x00000006
|
||||
|
@ -126,6 +122,123 @@ enum BankSwapSize
|
|||
ADDR_BANKSWAP_1KB = 1024,
|
||||
};
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @brief Enums that define max compressed fragments config
|
||||
****************************************************************************************************
|
||||
*/
|
||||
enum NumMaxCompressedFragmentsConfig
|
||||
{
|
||||
ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000,
|
||||
ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001,
|
||||
ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002,
|
||||
ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003,
|
||||
};
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @brief Enums that define num pipes config
|
||||
****************************************************************************************************
|
||||
*/
|
||||
enum NumPipesConfig
|
||||
{
|
||||
ADDR_CONFIG_1_PIPE = 0x00000000,
|
||||
ADDR_CONFIG_2_PIPE = 0x00000001,
|
||||
ADDR_CONFIG_4_PIPE = 0x00000002,
|
||||
ADDR_CONFIG_8_PIPE = 0x00000003,
|
||||
ADDR_CONFIG_16_PIPE = 0x00000004,
|
||||
ADDR_CONFIG_32_PIPE = 0x00000005,
|
||||
ADDR_CONFIG_64_PIPE = 0x00000006,
|
||||
};
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @brief Enums that define num banks config
|
||||
****************************************************************************************************
|
||||
*/
|
||||
enum NumBanksConfig
|
||||
{
|
||||
ADDR_CONFIG_1_BANK = 0x00000000,
|
||||
ADDR_CONFIG_2_BANK = 0x00000001,
|
||||
ADDR_CONFIG_4_BANK = 0x00000002,
|
||||
ADDR_CONFIG_8_BANK = 0x00000003,
|
||||
ADDR_CONFIG_16_BANK = 0x00000004,
|
||||
};
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @brief Enums that define num rb per shader engine config
|
||||
****************************************************************************************************
|
||||
*/
|
||||
enum NumRbPerShaderEngineConfig
|
||||
{
|
||||
ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000,
|
||||
ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001,
|
||||
ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002,
|
||||
};
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @brief Enums that define num shader engines config
|
||||
****************************************************************************************************
|
||||
*/
|
||||
enum NumShaderEnginesConfig
|
||||
{
|
||||
ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000,
|
||||
ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001,
|
||||
ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002,
|
||||
ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003,
|
||||
};
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @brief Enums that define pipe interleave size config
|
||||
****************************************************************************************************
|
||||
*/
|
||||
enum PipeInterleaveSizeConfig
|
||||
{
|
||||
ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000,
|
||||
ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001,
|
||||
ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002,
|
||||
ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003,
|
||||
};
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @brief Enums that define row size config
|
||||
****************************************************************************************************
|
||||
*/
|
||||
enum RowSizeConfig
|
||||
{
|
||||
ADDR_CONFIG_1KB_ROW = 0x00000000,
|
||||
ADDR_CONFIG_2KB_ROW = 0x00000001,
|
||||
ADDR_CONFIG_4KB_ROW = 0x00000002,
|
||||
};
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @brief Enums that define bank interleave size config
|
||||
****************************************************************************************************
|
||||
*/
|
||||
enum BankInterleaveSizeConfig
|
||||
{
|
||||
ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000,
|
||||
ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001,
|
||||
ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002,
|
||||
ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003,
|
||||
};
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @brief Enums that define engine tile size config
|
||||
****************************************************************************************************
|
||||
*/
|
||||
enum ShaderEngineTileSizeConfig
|
||||
{
|
||||
ADDR_CONFIG_SE_TILE_16 = 0x00000000,
|
||||
ADDR_CONFIG_SE_TILE_32 = 0x00000001,
|
||||
};
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @brief This class contains asic independent address lib functionalities
|
||||
|
|
|
@ -1281,36 +1281,54 @@ ADDR_E_RETURNCODE Lib::ComputeHtileInfo(
|
|||
|
||||
if (returnCode == ADDR_OK)
|
||||
{
|
||||
pOut->bpp = ComputeHtileInfo(pIn->flags,
|
||||
pIn->pitch,
|
||||
pIn->height,
|
||||
pIn->numSlices,
|
||||
pIn->isLinear,
|
||||
isWidth8,
|
||||
isHeight8,
|
||||
pIn->pTileInfo,
|
||||
&pOut->pitch,
|
||||
&pOut->height,
|
||||
&pOut->htileBytes,
|
||||
&pOut->macroWidth,
|
||||
&pOut->macroHeight,
|
||||
&pOut->sliceSize,
|
||||
&pOut->baseAlign);
|
||||
|
||||
if (pIn->flags.tcCompatible && (pIn->numSlices > 1))
|
||||
if (pIn->flags.tcCompatible)
|
||||
{
|
||||
pOut->sliceSize = pIn->pitch * pIn->height * 4 / (8 * 8);
|
||||
const UINT_32 sliceSize = pIn->pitch * pIn->height * 4 / (8 * 8);
|
||||
const UINT_32 align = HwlGetPipes(pIn->pTileInfo) * pIn->pTileInfo->banks * m_pipeInterleaveBytes;
|
||||
|
||||
const UINT_32 align = HwlGetPipes(pIn->pTileInfo) * pIn->pTileInfo->banks * m_pipeInterleaveBytes;
|
||||
|
||||
if ((pOut->sliceSize % align) == 0)
|
||||
if (pIn->numSlices > 1)
|
||||
{
|
||||
pOut->sliceInterleaved = FALSE;
|
||||
const UINT_32 surfBytes = (sliceSize * pIn->numSlices);
|
||||
|
||||
pOut->sliceSize = sliceSize;
|
||||
pOut->htileBytes = pIn->flags.skipTcCompatSizeAlign ?
|
||||
surfBytes : PowTwoAlign(surfBytes, align);
|
||||
pOut->sliceInterleaved = ((sliceSize % align) != 0) ? TRUE : FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
pOut->sliceInterleaved = TRUE;
|
||||
pOut->sliceSize = pIn->flags.skipTcCompatSizeAlign ?
|
||||
sliceSize : PowTwoAlign(sliceSize, align);
|
||||
pOut->htileBytes = pOut->sliceSize;
|
||||
pOut->sliceInterleaved = FALSE;
|
||||
}
|
||||
|
||||
pOut->nextMipLevelCompressible = ((sliceSize % align) == 0) ? TRUE : FALSE;
|
||||
|
||||
pOut->pitch = pIn->pitch;
|
||||
pOut->height = pIn->height;
|
||||
pOut->baseAlign = align;
|
||||
pOut->macroWidth = 0;
|
||||
pOut->macroHeight = 0;
|
||||
pOut->bpp = 32;
|
||||
}
|
||||
else
|
||||
{
|
||||
pOut->bpp = ComputeHtileInfo(pIn->flags,
|
||||
pIn->pitch,
|
||||
pIn->height,
|
||||
pIn->numSlices,
|
||||
pIn->isLinear,
|
||||
isWidth8,
|
||||
isHeight8,
|
||||
pIn->pTileInfo,
|
||||
&pOut->pitch,
|
||||
&pOut->height,
|
||||
&pOut->htileBytes,
|
||||
&pOut->macroWidth,
|
||||
&pOut->macroHeight,
|
||||
&pOut->sliceSize,
|
||||
&pOut->baseAlign);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -2162,6 +2180,8 @@ VOID Lib::HwlComputeXmaskCoordFromAddr(
|
|||
{
|
||||
UINT_32 pipe;
|
||||
UINT_32 numPipes;
|
||||
UINT_32 numGroupBits;
|
||||
(void)numGroupBits;
|
||||
UINT_32 numPipeBits;
|
||||
UINT_32 macroTilePitch;
|
||||
UINT_32 macroTileHeight;
|
||||
|
@ -2204,6 +2224,7 @@ VOID Lib::HwlComputeXmaskCoordFromAddr(
|
|||
//
|
||||
// Compute the number of group and pipe bits.
|
||||
//
|
||||
numGroupBits = Log2(m_pipeInterleaveBytes);
|
||||
numPipeBits = Log2(numPipes);
|
||||
|
||||
UINT_32 groupBits = 8 * m_pipeInterleaveBytes;
|
||||
|
@ -3504,6 +3525,10 @@ VOID Lib::ComputeMipLevel(
|
|||
ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in,out] Input structure
|
||||
) const
|
||||
{
|
||||
// Check if HWL has handled
|
||||
BOOL_32 hwlHandled = FALSE;
|
||||
(void)hwlHandled;
|
||||
|
||||
if (ElemLib::IsBlockCompressed(pIn->format))
|
||||
{
|
||||
if (pIn->mipLevel == 0)
|
||||
|
@ -3517,7 +3542,7 @@ VOID Lib::ComputeMipLevel(
|
|||
}
|
||||
}
|
||||
|
||||
HwlComputeMipLevel(pIn);
|
||||
hwlHandled = HwlComputeMipLevel(pIn);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -355,6 +355,11 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceAddrFromCoord(
|
|||
{
|
||||
returnCode = ComputeSurfaceAddrFromCoordTiled(&localIn, pOut);
|
||||
}
|
||||
|
||||
if (returnCode == ADDR_OK)
|
||||
{
|
||||
pOut->prtBlockIndex = static_cast<UINT_32>(pOut->addr / (64 * 1024));
|
||||
}
|
||||
}
|
||||
|
||||
return returnCode;
|
||||
|
@ -460,8 +465,7 @@ ADDR_E_RETURNCODE Lib::ComputeHtileInfo(
|
|||
*/
|
||||
ADDR_E_RETURNCODE Lib::ComputeHtileAddrFromCoord(
|
||||
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, ///< [in] input structure
|
||||
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut ///< [out] output structure
|
||||
) const
|
||||
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) ///< [out] output structure
|
||||
{
|
||||
ADDR_E_RETURNCODE returnCode;
|
||||
|
||||
|
@ -492,8 +496,7 @@ ADDR_E_RETURNCODE Lib::ComputeHtileAddrFromCoord(
|
|||
*/
|
||||
ADDR_E_RETURNCODE Lib::ComputeHtileCoordFromAddr(
|
||||
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, ///< [in] input structure
|
||||
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut ///< [out] output structure
|
||||
) const
|
||||
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) ///< [out] output structure
|
||||
{
|
||||
ADDR_E_RETURNCODE returnCode;
|
||||
|
||||
|
@ -560,8 +563,7 @@ ADDR_E_RETURNCODE Lib::ComputeCmaskInfo(
|
|||
*/
|
||||
ADDR_E_RETURNCODE Lib::ComputeCmaskAddrFromCoord(
|
||||
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, ///< [in] input structure
|
||||
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut ///< [out] output structure
|
||||
) const
|
||||
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) ///< [out] output structure
|
||||
{
|
||||
ADDR_E_RETURNCODE returnCode;
|
||||
|
||||
|
@ -780,8 +782,7 @@ ADDR_E_RETURNCODE Lib::ComputeDccInfo(
|
|||
*/
|
||||
ADDR_E_RETURNCODE Lib::ComputeDccAddrFromCoord(
|
||||
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, ///< [in] input structure
|
||||
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut ///< [out] output structure
|
||||
) const
|
||||
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) ///< [out] output structure
|
||||
{
|
||||
ADDR_E_RETURNCODE returnCode;
|
||||
|
||||
|
@ -1047,77 +1048,7 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceInfoLinear(
|
|||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] output structure
|
||||
) const
|
||||
{
|
||||
ADDR_E_RETURNCODE returnCode = ADDR_OK;
|
||||
|
||||
UINT_32 pitch = 0;
|
||||
UINT_32 actualHeight = 0;
|
||||
UINT_32 elementBytes = pIn->bpp >> 3;
|
||||
const UINT_32 alignment = pIn->flags.prt ? PrtAlignment : 256;
|
||||
|
||||
if (IsTex1d(pIn->resourceType))
|
||||
{
|
||||
if (pIn->height > 1)
|
||||
{
|
||||
returnCode = ADDR_INVALIDPARAMS;
|
||||
}
|
||||
else
|
||||
{
|
||||
const UINT_32 pitchAlignInElement = alignment / elementBytes;
|
||||
pitch = PowTwoAlign(pIn->width, pitchAlignInElement);
|
||||
actualHeight = pIn->numMipLevels;
|
||||
|
||||
if (pIn->flags.prt == FALSE)
|
||||
{
|
||||
returnCode = ApplyCustomizedPitchHeight(pIn, elementBytes, pitchAlignInElement,
|
||||
&pitch, &actualHeight);
|
||||
}
|
||||
|
||||
if (returnCode == ADDR_OK)
|
||||
{
|
||||
if (pOut->pMipInfo != NULL)
|
||||
{
|
||||
for (UINT_32 i = 0; i < pIn->numMipLevels; i++)
|
||||
{
|
||||
pOut->pMipInfo[i].offset = pitch * elementBytes * i;
|
||||
pOut->pMipInfo[i].pitch = pitch;
|
||||
pOut->pMipInfo[i].height = 1;
|
||||
pOut->pMipInfo[i].depth = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
returnCode = ComputeSurfaceLinearPadding(pIn, &pitch, &actualHeight, pOut->pMipInfo);
|
||||
}
|
||||
|
||||
if ((pitch == 0) || (actualHeight == 0))
|
||||
{
|
||||
returnCode = ADDR_INVALIDPARAMS;
|
||||
}
|
||||
|
||||
if (returnCode == ADDR_OK)
|
||||
{
|
||||
pOut->pitch = pitch;
|
||||
pOut->height = pIn->height;
|
||||
pOut->numSlices = pIn->numSlices;
|
||||
pOut->mipChainPitch = pitch;
|
||||
pOut->mipChainHeight = actualHeight;
|
||||
pOut->mipChainSlice = pOut->numSlices;
|
||||
pOut->epitchIsHeight = (pIn->numMipLevels > 1) ? TRUE : FALSE;
|
||||
pOut->sliceSize = static_cast<UINT_64>(pOut->pitch) * actualHeight * elementBytes;
|
||||
pOut->surfSize = pOut->sliceSize * pOut->numSlices;
|
||||
pOut->baseAlign = (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL) ? (pIn->bpp / 8) : alignment;
|
||||
pOut->blockWidth = (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL) ? 1 : (256 * 8 / pIn->bpp);
|
||||
pOut->blockHeight = 1;
|
||||
pOut->blockSlices = 1;
|
||||
}
|
||||
|
||||
// Post calculation validate
|
||||
ADDR_ASSERT(pOut->sliceSize > 0);
|
||||
|
||||
return returnCode;
|
||||
return HwlComputeSurfaceInfoLinear(pIn, pOut);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1170,6 +1101,8 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceAddrFromCoordLinear(
|
|||
{
|
||||
ADDR2_COMPUTE_SURFACE_INFO_INPUT localIn = {0};
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT localOut = {0};
|
||||
ADDR2_MIP_INFO mipInfo[MaxMipLevels];
|
||||
|
||||
localIn.bpp = pIn->bpp;
|
||||
localIn.flags = pIn->flags;
|
||||
localIn.width = Max(pIn->unalignedWidth, 1u);
|
||||
|
@ -1177,32 +1110,21 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceAddrFromCoordLinear(
|
|||
localIn.numSlices = Max(pIn->numSlices, 1u);
|
||||
localIn.numMipLevels = Max(pIn->numMipLevels, 1u);
|
||||
localIn.resourceType = pIn->resourceType;
|
||||
|
||||
if (localIn.numMipLevels <= 1)
|
||||
{
|
||||
localIn.pitchInElement = pIn->pitchInElement;
|
||||
}
|
||||
|
||||
localOut.pMipInfo = mipInfo;
|
||||
|
||||
returnCode = ComputeSurfaceInfoLinear(&localIn, &localOut);
|
||||
|
||||
if (returnCode == ADDR_OK)
|
||||
{
|
||||
UINT_32 elementBytes = pIn->bpp >> 3;
|
||||
UINT_64 sliceOffsetInSurf = localOut.sliceSize * pIn->slice;
|
||||
UINT_64 mipOffsetInSlice = 0;
|
||||
UINT_64 offsetInMip = 0;
|
||||
|
||||
if (IsTex1d(pIn->resourceType))
|
||||
{
|
||||
offsetInMip = static_cast<UINT_64>(pIn->x) * elementBytes;
|
||||
mipOffsetInSlice = static_cast<UINT_64>(pIn->mipId) * localOut.pitch * elementBytes;
|
||||
}
|
||||
else
|
||||
{
|
||||
UINT_64 mipStartHeight = SumGeo(localIn.height, pIn->mipId);
|
||||
mipOffsetInSlice = static_cast<UINT_64>(mipStartHeight) * localOut.pitch * elementBytes;
|
||||
offsetInMip = (pIn->y * localOut.pitch + pIn->x) * elementBytes;
|
||||
}
|
||||
|
||||
pOut->addr = sliceOffsetInSurf + mipOffsetInSlice + offsetInMip;
|
||||
pOut->addr = (localOut.sliceSize * pIn->slice) +
|
||||
mipInfo[pIn->mipId].offset +
|
||||
(pIn->y * mipInfo[pIn->mipId].pitch + pIn->x) * (pIn->bpp >> 3);
|
||||
pOut->bitPosition = 0;
|
||||
}
|
||||
else
|
||||
|
@ -1398,73 +1320,6 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceCoordFromAddrTiled(
|
|||
return returnCode;
|
||||
}
|
||||
|
||||
/**
|
||||
************************************************************************************************************************
|
||||
* Lib::ComputeSurfaceInfoLinear
|
||||
*
|
||||
* @brief
|
||||
* Internal function to calculate padding for linear swizzle 2D/3D surface
|
||||
*
|
||||
* @return
|
||||
* N/A
|
||||
************************************************************************************************************************
|
||||
*/
|
||||
ADDR_E_RETURNCODE Lib::ComputeSurfaceLinearPadding(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input srtucture
|
||||
UINT_32* pMipmap0PaddedWidth, ///< [out] padded width in element
|
||||
UINT_32* pSlice0PaddedHeight, ///< [out] padded height for HW
|
||||
ADDR2_MIP_INFO* pMipInfo ///< [out] per mip information
|
||||
) const
|
||||
{
|
||||
ADDR_E_RETURNCODE returnCode = ADDR_OK;
|
||||
|
||||
UINT_32 elementBytes = pIn->bpp >> 3;
|
||||
UINT_32 pitchAlignInElement = 0;
|
||||
|
||||
if (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL)
|
||||
{
|
||||
ADDR_ASSERT(pIn->numMipLevels <= 1);
|
||||
ADDR_ASSERT(pIn->numSlices <= 1);
|
||||
pitchAlignInElement = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
pitchAlignInElement = (256 / elementBytes);
|
||||
}
|
||||
|
||||
UINT_32 mipChainWidth = PowTwoAlign(pIn->width, pitchAlignInElement);
|
||||
UINT_32 slice0PaddedHeight = pIn->height;
|
||||
|
||||
returnCode = ApplyCustomizedPitchHeight(pIn, elementBytes, pitchAlignInElement,
|
||||
&mipChainWidth, &slice0PaddedHeight);
|
||||
|
||||
if (returnCode == ADDR_OK)
|
||||
{
|
||||
UINT_32 mipChainHeight = 0;
|
||||
UINT_32 mipHeight = pIn->height;
|
||||
|
||||
for (UINT_32 i = 0; i < pIn->numMipLevels; i++)
|
||||
{
|
||||
if (pMipInfo != NULL)
|
||||
{
|
||||
pMipInfo[i].offset = mipChainWidth * mipChainHeight * elementBytes;
|
||||
pMipInfo[i].pitch = mipChainWidth;
|
||||
pMipInfo[i].height = mipHeight;
|
||||
pMipInfo[i].depth = 1;
|
||||
}
|
||||
|
||||
mipChainHeight += mipHeight;
|
||||
mipHeight = RoundHalf(mipHeight);
|
||||
mipHeight = Max(mipHeight, 1u);
|
||||
}
|
||||
|
||||
*pMipmap0PaddedWidth = mipChainWidth;
|
||||
*pSlice0PaddedHeight = (pIn->numMipLevels > 1) ? mipChainHeight : slice0PaddedHeight;
|
||||
}
|
||||
|
||||
return returnCode;
|
||||
}
|
||||
|
||||
/**
|
||||
************************************************************************************************************************
|
||||
* Lib::ComputeBlockDimensionForSurf
|
||||
|
|
|
@ -103,63 +103,63 @@ public:
|
|||
// For data surface
|
||||
ADDR_E_RETURNCODE ComputeSurfaceInfo(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord(
|
||||
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
|
||||
ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr(
|
||||
const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
|
||||
const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
|
||||
|
||||
// For HTile
|
||||
ADDR_E_RETURNCODE ComputeHtileInfo(
|
||||
const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
|
||||
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
ADDR_E_RETURNCODE ComputeHtileAddrFromCoord(
|
||||
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
|
||||
|
||||
ADDR_E_RETURNCODE ComputeHtileCoordFromAddr(
|
||||
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const;
|
||||
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
|
||||
|
||||
// For CMask
|
||||
ADDR_E_RETURNCODE ComputeCmaskInfo(
|
||||
const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
|
||||
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
|
||||
|
||||
ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord(
|
||||
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
|
||||
|
||||
ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr(
|
||||
const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const;
|
||||
const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const;
|
||||
|
||||
// For FMask
|
||||
ADDR_E_RETURNCODE ComputeFmaskInfo(
|
||||
const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut);
|
||||
const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut);
|
||||
|
||||
ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord(
|
||||
const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
|
||||
ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr(
|
||||
const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
|
||||
const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
|
||||
|
||||
// For DCC key
|
||||
ADDR_E_RETURNCODE ComputeDccInfo(
|
||||
const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
|
||||
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
|
||||
|
||||
ADDR_E_RETURNCODE ComputeDccAddrFromCoord(
|
||||
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
|
||||
|
||||
// Misc
|
||||
ADDR_E_RETURNCODE ComputePipeBankXor(
|
||||
|
@ -197,6 +197,8 @@ protected:
|
|||
static const UINT_32 PrtAlignment = 64 * 1024;
|
||||
static const UINT_32 MaxMacroBits = 20;
|
||||
|
||||
static const UINT_32 MaxMipLevels = 16;
|
||||
|
||||
// Checking block size
|
||||
BOOL_32 IsBlock256b(AddrSwizzleMode swizzleMode) const
|
||||
{
|
||||
|
@ -402,32 +404,32 @@ protected:
|
|||
}
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord(
|
||||
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) const
|
||||
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut)
|
||||
{
|
||||
ADDR_NOT_IMPLEMENTED();
|
||||
return ADDR_NOTSUPPORTED;
|
||||
}
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
|
||||
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const
|
||||
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut)
|
||||
{
|
||||
ADDR_NOT_IMPLEMENTED();
|
||||
return ADDR_NOTSUPPORTED;
|
||||
}
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
|
||||
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const
|
||||
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut)
|
||||
{
|
||||
ADDR_NOT_IMPLEMENTED();
|
||||
return ADDR_NOTSUPPORTED;
|
||||
}
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
|
||||
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const
|
||||
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut)
|
||||
{
|
||||
ADDR_NOT_IMPLEMENTED();
|
||||
return ADDR_NOTSUPPORTED;
|
||||
|
@ -532,6 +534,14 @@ protected:
|
|||
return ADDR_NOTIMPLEMENTED;
|
||||
}
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
|
||||
{
|
||||
ADDR_NOT_IMPLEMENTED();
|
||||
return ADDR_NOTIMPLEMENTED;
|
||||
}
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
|
||||
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const
|
||||
|
@ -565,12 +575,6 @@ protected:
|
|||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
ADDR_E_RETURNCODE ComputeSurfaceLinearPadding(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
UINT_32* pMipmap0PaddedWidth,
|
||||
UINT_32* pSlice0PaddedHeight,
|
||||
ADDR2_MIP_INFO* pMipInfo = NULL) const;
|
||||
|
||||
ADDR_E_RETURNCODE ComputeSurfaceInfoTiled(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
|
@ -757,10 +761,10 @@ protected:
|
|||
|
||||
ADDR_E_RETURNCODE ApplyCustomizedPitchHeight(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
UINT_32 elementBytes,
|
||||
UINT_32 pitchAlignInElement,
|
||||
UINT_32* pPitch,
|
||||
UINT_32* pHeight) const;
|
||||
UINT_32 elementBytes,
|
||||
UINT_32 pitchAlignInElement,
|
||||
UINT_32* pPitch,
|
||||
UINT_32* pHeight) const;
|
||||
|
||||
VOID ComputeQbStereoInfo(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
|
|
|
@ -34,20 +34,20 @@ Coordinate::Coordinate()
|
|||
ord = 0;
|
||||
}
|
||||
|
||||
Coordinate::Coordinate(INT_8 c, UINT_32 n)
|
||||
Coordinate::Coordinate(INT_8 c, INT_32 n)
|
||||
{
|
||||
set(c,n);
|
||||
set(c, n);
|
||||
}
|
||||
|
||||
VOID Coordinate::set(INT_8 c, UINT_32 n)
|
||||
VOID Coordinate::set(INT_8 c, INT_32 n)
|
||||
{
|
||||
dim = c;
|
||||
ord = static_cast<INT_8>(n);
|
||||
}
|
||||
|
||||
UINT_32 Coordinate::ison(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m)
|
||||
UINT_32 Coordinate::ison(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m) const
|
||||
{
|
||||
UINT_32 bit = 1 << (UINT_32)ord;
|
||||
UINT_32 bit = static_cast<UINT_32>(1ull << static_cast<UINT_32>(ord));
|
||||
UINT_32 out = 0;
|
||||
|
||||
switch (dim)
|
||||
|
@ -234,7 +234,7 @@ UINT_32 CoordTerm::getsize()
|
|||
return num_coords;
|
||||
}
|
||||
|
||||
UINT_32 CoordTerm::getxor(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m)
|
||||
UINT_32 CoordTerm::getxor(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m) const
|
||||
{
|
||||
UINT_32 out = 0;
|
||||
for (UINT_32 i = 0; i < num_coords; i++)
|
||||
|
@ -386,7 +386,7 @@ UINT_32 CoordEq::getsize()
|
|||
return m_numBits;
|
||||
}
|
||||
|
||||
UINT_64 CoordEq::solve(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m)
|
||||
UINT_64 CoordEq::solve(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m) const
|
||||
{
|
||||
UINT_64 out = 0;
|
||||
for (UINT_32 i = 0; i < m_numBits; i++)
|
||||
|
@ -401,7 +401,7 @@ UINT_64 CoordEq::solve(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m)
|
|||
|
||||
VOID CoordEq::solveAddr(
|
||||
UINT_64 addr, UINT_32 sliceInM,
|
||||
UINT_32& x, UINT_32& y, UINT_32& z, UINT_32& s, UINT_32& m)
|
||||
UINT_32& x, UINT_32& y, UINT_32& z, UINT_32& s, UINT_32& m) const
|
||||
{
|
||||
UINT_32 xBitsValid = 0;
|
||||
UINT_32 yBitsValid = 0;
|
||||
|
|
|
@ -33,12 +33,12 @@ class Coordinate
|
|||
{
|
||||
public:
|
||||
Coordinate();
|
||||
Coordinate(INT_8 c, UINT_32 n);
|
||||
Coordinate(INT_8 c, INT_32 n);
|
||||
|
||||
VOID set(INT_8 c, UINT_32 n);
|
||||
UINT_32 ison(UINT_32 x, UINT_32 y, UINT_32 z = 0, UINT_32 s = 0, UINT_32 m = 0);
|
||||
INT_8 getdim();
|
||||
INT_8 getord();
|
||||
VOID set(INT_8 c, INT_32 n);
|
||||
UINT_32 ison(UINT_32 x, UINT_32 y, UINT_32 z = 0, UINT_32 s = 0, UINT_32 m = 0) const;
|
||||
INT_8 getdim();
|
||||
INT_8 getord();
|
||||
|
||||
BOOL_32 operator==(const Coordinate& b);
|
||||
BOOL_32 operator<(const Coordinate& b);
|
||||
|
@ -64,7 +64,7 @@ public:
|
|||
BOOL_32 Exists(Coordinate& co);
|
||||
VOID copyto(CoordTerm& cl);
|
||||
UINT_32 getsize();
|
||||
UINT_32 getxor(UINT_32 x, UINT_32 y, UINT_32 z = 0, UINT_32 s = 0, UINT_32 m = 0);
|
||||
UINT_32 getxor(UINT_32 x, UINT_32 y, UINT_32 z = 0, UINT_32 s = 0, UINT_32 m = 0) const;
|
||||
|
||||
VOID getsmallest(Coordinate& co);
|
||||
UINT_32 Filter(INT_8 f, Coordinate& co, UINT_32 start = 0, INT_8 axis = '\0');
|
||||
|
@ -87,9 +87,9 @@ public:
|
|||
BOOL_32 Exists(Coordinate& co);
|
||||
VOID resize(UINT_32 n);
|
||||
UINT_32 getsize();
|
||||
virtual UINT_64 solve(UINT_32 x, UINT_32 y, UINT_32 z = 0, UINT_32 s = 0, UINT_32 m = 0);
|
||||
virtual UINT_64 solve(UINT_32 x, UINT_32 y, UINT_32 z = 0, UINT_32 s = 0, UINT_32 m = 0) const;
|
||||
virtual VOID solveAddr(UINT_64 addr, UINT_32 sliceInM,
|
||||
UINT_32& x, UINT_32& y, UINT_32& z, UINT_32& s, UINT_32& m);
|
||||
UINT_32& x, UINT_32& y, UINT_32& z, UINT_32& s, UINT_32& m) const;
|
||||
|
||||
VOID copy(CoordEq& o, UINT_32 start = 0, UINT_32 num = 0xFFFFFFFF);
|
||||
VOID reverse(UINT_32 start = 0, UINT_32 num = 0xFFFFFFFF);
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -65,7 +65,9 @@ struct Gfx9ChipSettings
|
|||
// Misc configuration bits
|
||||
UINT_32 metaBaseAlignFix : 1;
|
||||
UINT_32 depthPipeXorDisable : 1;
|
||||
UINT_32 reserved2 : 30;
|
||||
UINT_32 htileAlignFix : 1;
|
||||
UINT_32 applyAliasFix : 1;
|
||||
UINT_32 reserved2 : 28;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -81,6 +83,28 @@ enum Gfx9DataType
|
|||
Gfx9DataFmask
|
||||
};
|
||||
|
||||
/**
|
||||
************************************************************************************************************************
|
||||
* @brief GFX9 meta equation parameters
|
||||
************************************************************************************************************************
|
||||
*/
|
||||
struct MetaEqParams
|
||||
{
|
||||
UINT_32 maxMip;
|
||||
UINT_32 elementBytesLog2;
|
||||
UINT_32 numSamplesLog2;
|
||||
ADDR2_META_FLAGS metaFlag;
|
||||
Gfx9DataType dataSurfaceType;
|
||||
AddrSwizzleMode swizzleMode;
|
||||
AddrResourceType resourceType;
|
||||
UINT_32 metaBlkWidthLog2;
|
||||
UINT_32 metaBlkHeightLog2;
|
||||
UINT_32 metaBlkDepthLog2;
|
||||
UINT_32 compBlkWidthLog2;
|
||||
UINT_32 compBlkHeightLog2;
|
||||
UINT_32 compBlkDepthLog2;
|
||||
};
|
||||
|
||||
/**
|
||||
************************************************************************************************************************
|
||||
* @brief This class is the GFX9 specific address library
|
||||
|
@ -139,31 +163,31 @@ protected:
|
|||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeHtileInfo(
|
||||
const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
|
||||
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo(
|
||||
const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
|
||||
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
|
||||
const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
|
||||
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
|
||||
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
|
||||
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
|
||||
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const;
|
||||
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord(
|
||||
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
|
||||
|
||||
virtual UINT_32 HwlGetEquationIndex(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
|
@ -206,17 +230,7 @@ protected:
|
|||
|
||||
if (IsXor(swizzleMode))
|
||||
{
|
||||
if (m_settings.isVega10 || m_settings.isRaven)
|
||||
{
|
||||
baseAlign = GetBlockSize(swizzleMode);
|
||||
}
|
||||
else
|
||||
{
|
||||
UINT_32 blockSizeLog2 = GetBlockSizeLog2(swizzleMode);
|
||||
UINT_32 pipeBits = GetPipeXorBits(blockSizeLog2);
|
||||
UINT_32 bankBits = GetBankXorBits(blockSizeLog2);
|
||||
baseAlign = 1 << (Min(blockSizeLog2, m_pipeInterleaveLog2 + pipeBits+ bankBits));
|
||||
}
|
||||
baseAlign = GetBlockSize(swizzleMode);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -249,6 +263,10 @@ protected:
|
|||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
|
||||
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
|
@ -352,6 +370,10 @@ protected:
|
|||
return compressBlkDim;
|
||||
}
|
||||
|
||||
|
||||
static const UINT_32 MaxSeLog2 = 3;
|
||||
static const UINT_32 MaxRbPerSeLog2 = 2;
|
||||
|
||||
static const Dim3d Block256_3dS[MaxNumOfBpp];
|
||||
static const Dim3d Block256_3dZ[MaxNumOfBpp];
|
||||
|
||||
|
@ -375,6 +397,8 @@ protected:
|
|||
// Equation lookup table according to bpp and tile index
|
||||
UINT_32 m_equationLookupTable[MaxRsrcType][MaxSwMode][MaxElementBytesLog2];
|
||||
|
||||
static const UINT_32 MaxCachedMetaEq = 2;
|
||||
|
||||
private:
|
||||
virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(
|
||||
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
|
||||
|
@ -382,7 +406,7 @@ private:
|
|||
virtual BOOL_32 HwlInitGlobalParams(
|
||||
const ADDR_CREATE_INPUT* pCreateIn);
|
||||
|
||||
static VOID GetRbEquation(CoordEq* pRbEq, UINT_32 rbPerSeLog2, UINT_32 seLog2);
|
||||
VOID GetRbEquation(CoordEq* pRbEq, UINT_32 rbPerSeLog2, UINT_32 seLog2) const;
|
||||
|
||||
VOID GetDataEquation(CoordEq* pDataEq, Gfx9DataType dataSurfaceType,
|
||||
AddrSwizzleMode swizzleMode, AddrResourceType resourceType,
|
||||
|
@ -393,7 +417,7 @@ private:
|
|||
UINT_32 numSamplesLog2, Gfx9DataType dataSurfaceType,
|
||||
AddrSwizzleMode swizzleMode, AddrResourceType resourceType) const;
|
||||
|
||||
VOID GetMetaEquation(CoordEq* pMetaEq, UINT_32 maxMip,
|
||||
VOID GenMetaEquation(CoordEq* pMetaEq, UINT_32 maxMip,
|
||||
UINT_32 elementBytesLog2, UINT_32 numSamplesLog2,
|
||||
ADDR2_META_FLAGS metaFlag, Gfx9DataType dataSurfaceType,
|
||||
AddrSwizzleMode swizzleMode, AddrResourceType resourceType,
|
||||
|
@ -401,6 +425,8 @@ private:
|
|||
UINT_32 metaBlkDepthLog2, UINT_32 compBlkWidthLog2,
|
||||
UINT_32 compBlkHeightLog2, UINT_32 compBlkDepthLog2) const;
|
||||
|
||||
const CoordEq* GetMetaEquation(const MetaEqParams& metaEqParams);
|
||||
|
||||
virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
|
||||
|
||||
VOID GetMetaMipInfo(UINT_32 numMipLevels, Dim3d* pMetaBlkDim,
|
||||
|
@ -408,7 +434,17 @@ private:
|
|||
UINT_32 mip0Width, UINT_32 mip0Height, UINT_32 mip0Depth,
|
||||
UINT_32* pNumMetaBlkX, UINT_32* pNumMetaBlkY, UINT_32* pNumMetaBlkZ) const;
|
||||
|
||||
ADDR_E_RETURNCODE ComputeSurfaceLinearPadding(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
UINT_32* pMipmap0PaddedWidth,
|
||||
UINT_32* pSlice0PaddedHeight,
|
||||
ADDR2_MIP_INFO* pMipInfo = NULL) const;
|
||||
|
||||
Gfx9ChipSettings m_settings;
|
||||
|
||||
CoordEq m_cachedMetaEq[MaxCachedMetaEq];
|
||||
MetaEqParams m_cachedMetaEqKey[MaxCachedMetaEq];
|
||||
UINT_32 m_metaEqOverrideIndex;
|
||||
};
|
||||
|
||||
} // V2
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,142 +0,0 @@
|
|||
/*
|
||||
* Copyright © 2017 Advanced Micro Devices, Inc.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sub license, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
|
||||
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||||
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial portions
|
||||
* of the Software.
|
||||
*/
|
||||
|
||||
// This class RB_MAP contains the top-level calculation functions which are used to generate rb id map based rb id equations
|
||||
|
||||
#ifndef __RB_MAP_H
|
||||
#define __RB_MAP_H
|
||||
|
||||
#include "coord.h"
|
||||
|
||||
class RB_MAP
|
||||
{
|
||||
public:
|
||||
|
||||
enum MAX_VALUES {
|
||||
MAX_SES_LOG2 = 3,
|
||||
MAX_RBS_LOG2 = 2
|
||||
};
|
||||
|
||||
enum COMPRESSED_DATABLOCKS_IN_METABLOCK_PER_RB_LOG2 {
|
||||
COMPRESSED_DATABLOCKS_IN_METABLOCK_PER_RB_LOG2_2D = 10,
|
||||
COMPRESSED_DATABLOCKS_IN_METABLOCK_PER_RB_LOG2_3D = 18
|
||||
};
|
||||
|
||||
RB_MAP(void);
|
||||
|
||||
void Get_Comp_Block_Screen_Space( CoordEq& addr, int bytes_log2, int* w, int* h, int* d = NULL);
|
||||
|
||||
void Get_Meta_Block_Screen_Space( int num_comp_blocks_log2, bool is_thick, bool y_biased,
|
||||
int comp_block_width_log2, int comp_block_height_log2, int comp_block_depth_log2,
|
||||
int& meta_block_width_log2, int& meta_block_height_log2, int& meta_block_depth_log2 );
|
||||
void cap_pipe( int xmode, bool is_thick, int& num_ses_log2, int bpp_log2, int num_samples_log2, int pipe_interleave_log2,
|
||||
int& block_size_log2, int& num_pipes_log2 );
|
||||
|
||||
void Get_Data_Offset_Equation( CoordEq& data_eq, int data_type, int bpp_log2, int num_samples_log2, int block_size_log2 );
|
||||
|
||||
void Get_RB_Equation( CoordEq& rb_equation, int num_ses_log2, int num_rbs_log2 );
|
||||
|
||||
void Get_Pipe_Equation( CoordEq& pipe_equation, CoordEq& addr,
|
||||
int pipe_interleave_log2,
|
||||
int num_pipes_log2,
|
||||
int block_size_log2,
|
||||
int num_samples_log2,
|
||||
int xmode, int data_type
|
||||
);
|
||||
|
||||
void get_meta_miptail_coord( int& x, int& y, int& z, int mip_in_tail, int blk_width_log2, int blk_height_log2, int blk_depth_log2 );
|
||||
|
||||
void get_mip_coord( int& x, int& y, int& z, int mip,
|
||||
int meta_blk_width_log2, int meta_blk_height_log2, int meta_blk_depth_log2,
|
||||
int data_blk_width_log2, int data_blk_height_log2,
|
||||
int& surf_width, int& surf_height, int& surf_depth, int epitch, int max_mip,
|
||||
int data_type, int bpp_log2, bool meta_linear );
|
||||
|
||||
void get_mip_coord_linear( int& x, int& y, int& z, int mip, int data_blk_width_log2, int data_blk_height_log2,
|
||||
int& surf_width, int& surf_height, int& surf_depth, int epitch, int max_mip, int data_type, int bpp_log2 );
|
||||
|
||||
void get_mip_coord_nonlinear( int& x, int& y, int& z, int mip, int meta_blk_width_log2, int meta_blk_height_log2, int meta_blk_depth_log2,
|
||||
int& surf_width, int& surf_height, int& surf_depth, int epitch, int max_mip, int data_type );
|
||||
|
||||
void get_meta_eq( CoordEq& metaaddr, int max_mip, int num_ses_log2, int num_rbs_log2, int &num_pipes_log2,
|
||||
int block_size_log2, int bpp_log2, int num_samples_log2, int max_comp_frag_log2,
|
||||
int pipe_interleave_log2, int xmode, int data_type, int meta_alignment, bool meta_linear);
|
||||
|
||||
#if 0
|
||||
long get_meta_addr( int x, int y, int z, int s, int mip,
|
||||
int surf_width, int surf_height, int surf_depth, int epitch,
|
||||
long surf_base, int pipe_xor, int max_mip,
|
||||
int num_ses_log2, int num_rbs_log2, int num_pipes_log2,
|
||||
int block_size_log2, int bpp_log2, int num_samples_log2, int max_comp_frag_log2,
|
||||
int pipe_interleave_log2, int xmode, int data_type, int meta_alignment, bool meta_linear);
|
||||
#endif
|
||||
|
||||
long get_meta_addr_calc( int x, int y, int z, int s,
|
||||
long surf_base, int element_bytes_log2, int num_samples_log2, int max_comp_frag_log2,
|
||||
long pitch, long slice,
|
||||
int max_mip,
|
||||
//int swizzle_mode,
|
||||
int xmode, int pipe_xor, int block_size_log2,
|
||||
/*int num_banks_log2,*/ int num_pipes_log2,
|
||||
int pipe_interleave_log2, int meta_alignment, int dim_type, int x_mip_org, int y_mip_org,
|
||||
int z_mip_org, int num_ses_log2, int num_rbs_log2, /*bool se_affinity_enable,*/ int data_type,
|
||||
int l2_metablk_w, int l2_metablk_h, int l2_metablk_d, bool meta_linear);
|
||||
|
||||
void Initialize(void);
|
||||
|
||||
public:
|
||||
enum XOR_RANGE {
|
||||
NONE = 0,
|
||||
XOR = 1,
|
||||
PRT = 2
|
||||
};
|
||||
|
||||
|
||||
enum DATA_TYPE_ENUM {
|
||||
DATA_COLOR1D,
|
||||
DATA_COLOR2D,
|
||||
DATA_COLOR3D_S,
|
||||
DATA_COLOR3D_Z,
|
||||
DATA_Z_STENCIL,
|
||||
DATA_FMASK,
|
||||
DATA_COLOR2D_LINEAR,
|
||||
DATA_COLOR3D_D_NOT_USED // should not be used; use COLOR2D instead
|
||||
};
|
||||
|
||||
enum META_ALIGNMENT {
|
||||
META_ALIGN_NONE,
|
||||
META_ALIGN_PIPE,
|
||||
META_ALIGN_RB,
|
||||
META_ALIGN_PIPE_RB
|
||||
};
|
||||
|
||||
CoordEq rb_equation[MAX_SES_LOG2+1][MAX_RBS_LOG2+1];
|
||||
CoordEq zaddr [4][4];
|
||||
CoordEq caddr [5][4];
|
||||
CoordEq c3addr[5][2];
|
||||
};
|
||||
|
||||
#endif
|
|
@ -27,6 +27,14 @@
|
|||
* of the Software.
|
||||
*/
|
||||
|
||||
#include "util/u_endian.h"
|
||||
|
||||
#if defined(PIPE_ARCH_LITTLE_ENDIAN)
|
||||
#define LITTLEENDIAN_CPU
|
||||
#elif defined(PIPE_ARCH_BIG_ENDIAN)
|
||||
#define BIGENDIAN_CPU
|
||||
#endif
|
||||
|
||||
//
|
||||
// Make sure the necessary endian defines are there.
|
||||
//
|
||||
|
|
|
@ -27,6 +27,14 @@
|
|||
* of the Software.
|
||||
*/
|
||||
|
||||
#include "util/u_endian.h"
|
||||
|
||||
#if defined(PIPE_ARCH_LITTLE_ENDIAN)
|
||||
#define LITTLEENDIAN_CPU
|
||||
#elif defined(PIPE_ARCH_BIG_ENDIAN)
|
||||
#define BIGENDIAN_CPU
|
||||
#endif
|
||||
|
||||
//
|
||||
// Make sure the necessary endian defines are there.
|
||||
//
|
||||
|
|
|
@ -1,129 +0,0 @@
|
|||
/*
|
||||
* Copyright © 2014 Advanced Micro Devices, Inc.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sub license, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
|
||||
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||||
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial portions
|
||||
* of the Software.
|
||||
*/
|
||||
#ifndef _lnx_common_defs_h_
|
||||
#define _lnx_common_defs_h_
|
||||
|
||||
#if DBG
|
||||
#include <stdarg.h> // We do not have any choice: need variable
|
||||
// number of parameters support for debug
|
||||
// build.
|
||||
#endif // #if DBG
|
||||
|
||||
//
|
||||
// -------------- External functions from Linux kernel driver ----------------
|
||||
//
|
||||
// Note: The definitions/declararions below must match the original ones.
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef unsigned long __ke_size_t; // as it is defined in firegl_public.h
|
||||
typedef int __kernel_ptrdiff_t; // as it is defined in posix_types.h
|
||||
|
||||
|
||||
#if !defined(ATI_API_CALL)
|
||||
#define ATI_API_CALL __attribute__((regparm(0)))
|
||||
#endif
|
||||
|
||||
extern void * ATI_API_CALL __ke_memset(void* s, int c, __ke_size_t count);
|
||||
extern void * ATI_API_CALL __ke_memcpy(void* d, const void* s, __ke_size_t count);
|
||||
extern ATI_API_CALL __ke_size_t __ke_strlen(const char *s);
|
||||
extern char* ATI_API_CALL __ke_strcpy(char* d, const char* s);
|
||||
extern char* ATI_API_CALL __ke_strncpy(char* d, const char* s, __ke_size_t count);
|
||||
extern void __ke_printk(const char* fmt, ...);
|
||||
|
||||
extern int ATI_API_CALL __ke_snprintf(char* buf, __ke_size_t size, const char* fmt, ...);
|
||||
extern int ATI_API_CALL KCL_CopyFromUserSpace(void* to, const void* from, __ke_size_t size);
|
||||
extern int ATI_API_CALL KCL_CopyToUserSpace(void* to, const void* from, __ke_size_t size);
|
||||
#define __ke_copy_from_user KCL_CopyFromUserSpace
|
||||
#define __ke_copy_to_user KCL_CopyToUserSpace
|
||||
extern int ATI_API_CALL __ke_verify_area(int type, const void * addr, unsigned long size);
|
||||
|
||||
extern unsigned long ATI_API_CALL KAS_GetTickCounter(void);
|
||||
extern unsigned long ATI_API_CALL KAS_GetTicksPerSecond(void);
|
||||
|
||||
|
||||
#if DBG
|
||||
extern int ATI_API_CALL __ke_vsnprintf(char *buf, __ke_size_t size, const char *fmt, va_list ap);
|
||||
#define vsnprintf(_dst, _size, _fmt, varg) __ke_snprintf(_dst, _size, _fmt, varg)
|
||||
#endif // #if DBG
|
||||
|
||||
|
||||
// Note: This function is not defined in firegl_public.h.
|
||||
void firegl_hardwareHangRecovery(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
//
|
||||
// -------------------------- C/C++ standard typedefs ----------------------------
|
||||
//
|
||||
#ifdef __SIZE_TYPE__
|
||||
typedef __SIZE_TYPE__ size_t;
|
||||
#else // #ifdef __SIZE_TYPE__
|
||||
typedef unsigned int size_t;
|
||||
#endif // #ifdef __SIZE_TYPE__
|
||||
|
||||
#ifdef __PTRDIFF_TYPE__
|
||||
typedef __PTRDIFF_TYPE__ ptrdiff_t;
|
||||
#else // #ifdef __PTRDIFF_TYPE__
|
||||
typedef int ptrdiff_t;
|
||||
#endif // #ifdef __PTRDIFF_TYPE__
|
||||
|
||||
#ifndef NULL
|
||||
#ifdef __cplusplus
|
||||
#define NULL __null
|
||||
#else
|
||||
#define NULL ((void *)0)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
// ------------------------- C/C++ standard macros ---------------------------
|
||||
//
|
||||
|
||||
#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) // as it is defined in stddef.h
|
||||
#define CHAR_BIT 8 // as it is defined in limits.h
|
||||
|
||||
//
|
||||
// --------------------------------- C RTL -----------------------------------
|
||||
//
|
||||
|
||||
#define memset(_p, _v, _n) __ke_memset(_p, _v, _n)
|
||||
#define memcpy(_d, _s, _n) __ke_memcpy(_d, _s, _n)
|
||||
#define strlen(_s) __ke_strlen(_s)
|
||||
#define strcpy(_d, _s) __ke_strcpy(_d, _s)
|
||||
#define strncpy(_d, _s, _n) __ke_strncpy(_d, _s, _n)
|
||||
// Note: C99 supports macros with variable number of arguments. GCC also supports this C99 feature as
|
||||
// C++ extension.
|
||||
#define snprintf(_dst, _size, _fmt, arg...) __ke_snprintf(_dst, _size, _fmt, ##arg)
|
||||
|
||||
|
||||
#endif // #ifdef _lnx_common_defs_h_
|
||||
|
|
@ -38,11 +38,9 @@ files_addrlib = files(
|
|||
'gfx9/coord.h',
|
||||
'gfx9/gfx9addrlib.cpp',
|
||||
'gfx9/gfx9addrlib.h',
|
||||
'gfx9/rbmap.cpp',
|
||||
'gfx9/rbmap.h',
|
||||
'amdgpu_asic_addr.h',
|
||||
'inc/chip/gfx9/gfx9_gb_reg.h',
|
||||
'inc/chip/r800/si_gb_reg.h',
|
||||
'inc/lnx_common_defs.h',
|
||||
'r800/chip/si_ci_vi_merged_enum.h',
|
||||
'r800/ciaddrlib.cpp',
|
||||
'r800/ciaddrlib.h',
|
||||
|
|
|
@ -35,15 +35,7 @@
|
|||
|
||||
#include "si_gb_reg.h"
|
||||
|
||||
#include "si_ci_vi_merged_enum.h"
|
||||
|
||||
#if BRAHMA_BUILD
|
||||
#include "amdgpu_id.h"
|
||||
#else
|
||||
#include "ci_id.h"
|
||||
#include "kv_id.h"
|
||||
#include "vi_id.h"
|
||||
#endif
|
||||
#include "amdgpu_asic_addr.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
@ -188,7 +180,6 @@ CiLib::CiLib(const Client* pClient)
|
|||
m_allowNonDispThickModes(FALSE)
|
||||
{
|
||||
m_class = CI_ADDRLIB;
|
||||
memset(&m_settings, 0, sizeof(m_settings));
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -450,7 +441,6 @@ BOOL_32 CiLib::HwlInitGlobalParams(
|
|||
// read the correct pipes from tile mode table
|
||||
if (m_settings.isHawaii)
|
||||
{
|
||||
// Hawaii has 16-pipe, see GFXIP_Config_Summary.xls
|
||||
m_pipes = 16;
|
||||
}
|
||||
else if (m_settings.isBonaire || m_settings.isSpectre)
|
||||
|
@ -600,9 +590,9 @@ INT_32 CiLib::HwlPostCheckTileIndex(
|
|||
****************************************************************************************************
|
||||
*/
|
||||
ADDR_E_RETURNCODE CiLib::HwlSetupTileCfg(
|
||||
UINT_32 bpp, ///< [in] Bits per pixel
|
||||
INT_32 index, ///< [in] Tile index
|
||||
INT_32 macroModeIndex, ///< [in] Index in macro tile mode table(CI)
|
||||
UINT_32 bpp, ///< Bits per pixel
|
||||
INT_32 index, ///< Tile index
|
||||
INT_32 macroModeIndex, ///< Index in macro tile mode table(CI)
|
||||
ADDR_TILEINFO* pInfo, ///< [out] Tile Info
|
||||
AddrTileMode* pMode, ///< [out] Tile mode
|
||||
AddrTileType* pType ///< [out] Tile type
|
||||
|
@ -711,13 +701,12 @@ ADDR_E_RETURNCODE CiLib::HwlComputeSurfaceInfo(
|
|||
|
||||
ADDR_E_RETURNCODE retCode = SiLib::HwlComputeSurfaceInfo(pIn, pOut);
|
||||
|
||||
|
||||
if ((pIn->mipLevel > 0) &&
|
||||
(pOut->tcCompatible == TRUE) &&
|
||||
(pOut->tileMode != pIn->tileMode) &&
|
||||
(m_settings.isVolcanicIslands == TRUE))
|
||||
{
|
||||
CheckTcCompatibility(pOut->pTileInfo, pIn->bpp, pOut->tileMode, pOut->tileType, pOut);
|
||||
pOut->tcCompatible = CheckTcCompatibility(pOut->pTileInfo, pIn->bpp, pOut->tileMode, pOut->tileType, pOut);
|
||||
}
|
||||
|
||||
if (pOut->macroModeIndex == TileIndexNoMacroIndex)
|
||||
|
@ -1572,7 +1561,7 @@ VOID CiLib::HwlSetupTileInfo(
|
|||
|
||||
if (flags.tcCompatible)
|
||||
{
|
||||
CheckTcCompatibility(pTileInfo, bpp, tileMode, inTileType, pOut);
|
||||
flags.tcCompatible = CheckTcCompatibility(pTileInfo, bpp, tileMode, inTileType, pOut);
|
||||
}
|
||||
|
||||
pOut->tcCompatible = flags.tcCompatible;
|
||||
|
@ -2271,19 +2260,21 @@ BOOL_32 CiLib::DepthStencilTileCfgMatch(
|
|||
* CiLib::DepthStencilTileCfgMatch
|
||||
*
|
||||
* @brief
|
||||
* Turn off TcCompatible if requirement is not met
|
||||
* Check if tc compatibility is available
|
||||
* @return
|
||||
* N/A
|
||||
* If tc compatibility is not available
|
||||
****************************************************************************************************
|
||||
*/
|
||||
VOID CiLib::CheckTcCompatibility(
|
||||
const ADDR_TILEINFO* pTileInfo, ///< [in] input tile info
|
||||
UINT_32 bpp, ///< [in] Bits per pixel
|
||||
AddrTileMode tileMode, ///< [in] input tile mode
|
||||
AddrTileType tileType, ///< [in] input tile type
|
||||
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] out structure
|
||||
BOOL_32 CiLib::CheckTcCompatibility(
|
||||
const ADDR_TILEINFO* pTileInfo, ///< [in] input tile info
|
||||
UINT_32 bpp, ///< [in] Bits per pixel
|
||||
AddrTileMode tileMode, ///< [in] input tile mode
|
||||
AddrTileType tileType, ///< [in] input tile type
|
||||
const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in] output surf info
|
||||
) const
|
||||
{
|
||||
BOOL_32 tcCompatible = TRUE;
|
||||
|
||||
if (IsMacroTiled(tileMode))
|
||||
{
|
||||
if (tileType != ADDR_DEPTH_SAMPLE_ORDER)
|
||||
|
@ -2309,7 +2300,7 @@ VOID CiLib::CheckTcCompatibility(
|
|||
|
||||
if (m_rowSize < colorTileSplit)
|
||||
{
|
||||
pOut->tcCompatible = FALSE;
|
||||
tcCompatible = FALSE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -2317,8 +2308,10 @@ VOID CiLib::CheckTcCompatibility(
|
|||
else
|
||||
{
|
||||
// Client should not enable tc compatible for linear and 1D tile modes.
|
||||
pOut->tcCompatible = FALSE;
|
||||
tcCompatible = FALSE;
|
||||
}
|
||||
|
||||
return tcCompatible;
|
||||
}
|
||||
|
||||
} // V1
|
||||
|
|
|
@ -42,37 +42,6 @@ namespace Addr
|
|||
namespace V1
|
||||
{
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @brief CI specific settings structure.
|
||||
****************************************************************************************************
|
||||
*/
|
||||
struct CIChipSettings
|
||||
{
|
||||
struct
|
||||
{
|
||||
UINT_32 isSeaIsland : 1;
|
||||
UINT_32 isBonaire : 1;
|
||||
UINT_32 isKaveri : 1;
|
||||
UINT_32 isSpectre : 1;
|
||||
UINT_32 isSpooky : 1;
|
||||
UINT_32 isKalindi : 1;
|
||||
// Hawaii is GFXIP 7.2
|
||||
UINT_32 isHawaii : 1;
|
||||
|
||||
// VI
|
||||
UINT_32 isVolcanicIslands : 1;
|
||||
UINT_32 isIceland : 1;
|
||||
UINT_32 isTonga : 1;
|
||||
UINT_32 isFiji : 1;
|
||||
UINT_32 isPolaris10 : 1;
|
||||
UINT_32 isPolaris11 : 1;
|
||||
UINT_32 isPolaris12 : 1;
|
||||
// VI fusion (Carrizo)
|
||||
UINT_32 isCarrizo : 1;
|
||||
};
|
||||
};
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @brief This class is the CI specific address library
|
||||
|
@ -208,9 +177,8 @@ private:
|
|||
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
VOID CheckTcCompatibility(
|
||||
const ADDR_TILEINFO* pTileInfo, UINT_32 bpp, AddrTileMode tileMode,
|
||||
AddrTileType tileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
BOOL_32 CheckTcCompatibility(const ADDR_TILEINFO* pTileInfo, UINT_32 bpp, AddrTileMode tileMode,
|
||||
AddrTileType tileType, const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
static const UINT_32 MacroTileTableSize = 16;
|
||||
static const UINT_32 PrtMacroModeOffset = MacroTileTableSize / 2;
|
||||
|
@ -221,8 +189,6 @@ private:
|
|||
ADDR_TILEINFO m_macroTileTable[MacroTileTableSize];
|
||||
UINT_32 m_noOfMacroEntries;
|
||||
BOOL_32 m_allowNonDispThickModes;
|
||||
|
||||
CIChipSettings m_settings;
|
||||
};
|
||||
|
||||
} // V1
|
||||
|
|
|
@ -739,13 +739,12 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMicroTiled(
|
|||
|
||||
AdjustPitchAlignment(flags, pPitchAlign);
|
||||
|
||||
// ECR#393489
|
||||
// Workaround 2 for 1D tiling - There is HW bug for Carrizo
|
||||
// Workaround 2 for 1D tiling - There is HW bug for Carrizo,
|
||||
// where it requires the following alignments for 1D tiling.
|
||||
if (flags.czDispCompatible && (mipLevel == 0))
|
||||
{
|
||||
*pBaseAlign = PowTwoAlign(*pBaseAlign, 4096); //Base address MOD 4096 = 0
|
||||
*pPitchAlign = PowTwoAlign(*pPitchAlign, 512 / (BITS_TO_BYTES(bpp))); //(8 lines * pitch * bytes per pixel) MOD 4096 = 0
|
||||
*pPitchAlign = PowTwoAlign(*pPitchAlign, 512 / (BITS_TO_BYTES(bpp))); //(8 lines * pitch * bytes per pixel) MOD 4096 = 0
|
||||
}
|
||||
// end Carrizo workaround for 1D tilling
|
||||
|
||||
|
@ -1091,6 +1090,8 @@ AddrTileMode EgBasedLib::ComputeSurfaceMipLevelTileMode(
|
|||
ADDR_TILEINFO* pTileInfo ///< [in] ptr to bank structure
|
||||
) const
|
||||
{
|
||||
UINT_64 bytesPerSlice;
|
||||
(void)bytesPerSlice;
|
||||
UINT_32 bytesPerTile;
|
||||
|
||||
AddrTileMode expTileMode = baseTileMode;
|
||||
|
@ -1100,6 +1101,7 @@ AddrTileMode EgBasedLib::ComputeSurfaceMipLevelTileMode(
|
|||
//
|
||||
// Compute the size of a slice.
|
||||
//
|
||||
bytesPerSlice = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp * numSamples);
|
||||
bytesPerTile = BITS_TO_BYTES(MicroTilePixels * microTileThickness * NextPow2(bpp) * numSamples);
|
||||
|
||||
//
|
||||
|
@ -1329,12 +1331,6 @@ UINT_64 EgBasedLib::DispatchComputeSurfaceAddrFromCoord(
|
|||
UINT_32* pBitPosition = &pOut->bitPosition;
|
||||
UINT_64 addr;
|
||||
|
||||
#if ADDR_AM_BUILD
|
||||
UINT_32 addr5Bit = 0;
|
||||
UINT_32 addr5Swizzle = pIn->addr5Swizzle;
|
||||
BOOL_32 is32ByteTile = pIn->is32ByteTile;
|
||||
#endif
|
||||
|
||||
// ADDR_DEPTH_SAMPLE_ORDER = non-disp + depth-sample-order
|
||||
if (microTileType == ADDR_DEPTH_SAMPLE_ORDER)
|
||||
{
|
||||
|
@ -1439,23 +1435,6 @@ UINT_64 EgBasedLib::DispatchComputeSurfaceAddrFromCoord(
|
|||
break;
|
||||
}
|
||||
|
||||
#if ADDR_AM_BUILD
|
||||
if (m_chipFamily >= ADDR_CHIP_FAMILY_NI)
|
||||
{
|
||||
if (addr5Swizzle && isDepthSampleOrder && is32ByteTile)
|
||||
{
|
||||
UINT_32 tx = x >> 3;
|
||||
UINT_32 ty = y >> 3;
|
||||
UINT_32 tileBits = ((ty&0x3) << 2) | (tx&0x3);
|
||||
|
||||
tileBits = tileBits & addr5Swizzle;
|
||||
addr5Bit = XorReduce(tileBits, 4);
|
||||
|
||||
addr = addr | static_cast<UINT_64>(addr5Bit << 5);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
|
@ -2751,6 +2730,8 @@ ADDR_E_RETURNCODE EgBasedLib::HwlComputeBaseSwizzle(
|
|||
{ 0, 7, 14, 5, 12, 3, 10, 1, 8, 15, 6, 13, 4, 11, 2, 9 }, // ADDR_SURF_16_BANK
|
||||
};
|
||||
|
||||
UINT_32 pipes = HwlGetPipes(pTileInfo);
|
||||
(void)pipes;
|
||||
UINT_32 banks = pTileInfo ? pTileInfo->banks : 2;
|
||||
UINT_32 hwNumBanks;
|
||||
|
||||
|
@ -3379,20 +3360,6 @@ ADDR_E_RETURNCODE EgBasedLib::HwlComputeFmaskAddrFromCoord(
|
|||
{
|
||||
ADDR_E_RETURNCODE retCode = ADDR_OK;
|
||||
|
||||
#if ADDR_AM_BUILD
|
||||
if ((pIn->x > pIn->pitch) ||
|
||||
(pIn->y > pIn->height) ||
|
||||
(pIn->numSamples > m_maxSamples) ||
|
||||
(pIn->sample >= m_maxSamples))
|
||||
{
|
||||
retCode = ADDR_INVALIDPARAMS;
|
||||
}
|
||||
else
|
||||
{
|
||||
pOut->addr = DispatchComputeFmaskAddrFromCoord(pIn, pOut);
|
||||
}
|
||||
#endif
|
||||
|
||||
return retCode;
|
||||
}
|
||||
|
||||
|
@ -3412,618 +3379,9 @@ ADDR_E_RETURNCODE EgBasedLib::HwlComputeFmaskCoordFromAddr(
|
|||
{
|
||||
ADDR_E_RETURNCODE retCode = ADDR_OK;
|
||||
|
||||
#if ADDR_AM_BUILD
|
||||
if ((pIn->bitPosition >= 8) ||
|
||||
(pIn->numSamples > m_maxSamples))
|
||||
{
|
||||
retCode = ADDR_INVALIDPARAMS;
|
||||
}
|
||||
else
|
||||
{
|
||||
DispatchComputeFmaskCoordFromAddr(pIn, pOut);
|
||||
}
|
||||
#endif
|
||||
|
||||
return retCode;
|
||||
}
|
||||
|
||||
#if ADDR_AM_BUILD
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* EgBasedLib::DispatchComputeFmaskAddrFromCoord
|
||||
*
|
||||
* @brief
|
||||
* Computes the FMASK address and bit position from a coordinate.
|
||||
* @return
|
||||
* The byte address
|
||||
****************************************************************************************************
|
||||
*/
|
||||
UINT_64 EgBasedLib::DispatchComputeFmaskAddrFromCoord(
|
||||
const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, ///< [in] input structure
|
||||
ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut ///< [out] output structure
|
||||
) const
|
||||
{
|
||||
UINT_32 x = pIn->x;
|
||||
UINT_32 y = pIn->y;
|
||||
UINT_32 slice = pIn->slice;
|
||||
UINT_32 sample = pIn->sample;
|
||||
UINT_32 plane = pIn->plane;
|
||||
UINT_32 pitch = pIn->pitch;
|
||||
UINT_32 height = pIn->height;
|
||||
UINT_32 numSamples = pIn->numSamples;
|
||||
AddrTileMode tileMode = pIn->tileMode;
|
||||
BOOL_32 ignoreSE = pIn->ignoreSE;
|
||||
ADDR_TILEINFO* pTileInfo = pIn->pTileInfo;
|
||||
BOOL_32 resolved = pIn->resolved;
|
||||
|
||||
UINT_32* pBitPosition = &pOut->bitPosition;
|
||||
UINT_64 addr = 0;
|
||||
|
||||
ADDR_ASSERT(numSamples > 1);
|
||||
ADDR_ASSERT(Thickness(tileMode) == 1);
|
||||
|
||||
switch (tileMode)
|
||||
{
|
||||
case ADDR_TM_1D_TILED_THIN1:
|
||||
addr = ComputeFmaskAddrFromCoordMicroTiled(x,
|
||||
y,
|
||||
slice,
|
||||
sample,
|
||||
plane,
|
||||
pitch,
|
||||
height,
|
||||
numSamples,
|
||||
tileMode,
|
||||
resolved,
|
||||
pBitPosition);
|
||||
break;
|
||||
case ADDR_TM_2D_TILED_THIN1: //fall through
|
||||
case ADDR_TM_3D_TILED_THIN1:
|
||||
UINT_32 pipeSwizzle;
|
||||
UINT_32 bankSwizzle;
|
||||
|
||||
if (m_configFlags.useCombinedSwizzle)
|
||||
{
|
||||
ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo,
|
||||
&bankSwizzle, &pipeSwizzle);
|
||||
}
|
||||
else
|
||||
{
|
||||
pipeSwizzle = pIn->pipeSwizzle;
|
||||
bankSwizzle = pIn->bankSwizzle;
|
||||
}
|
||||
|
||||
addr = ComputeFmaskAddrFromCoordMacroTiled(x,
|
||||
y,
|
||||
slice,
|
||||
sample,
|
||||
plane,
|
||||
pitch,
|
||||
height,
|
||||
numSamples,
|
||||
tileMode,
|
||||
pipeSwizzle,
|
||||
bankSwizzle,
|
||||
ignoreSE,
|
||||
pTileInfo,
|
||||
resolved,
|
||||
pBitPosition);
|
||||
break;
|
||||
default:
|
||||
*pBitPosition = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* EgBasedLib::ComputeFmaskAddrFromCoordMicroTiled
|
||||
*
|
||||
* @brief
|
||||
* Computes the FMASK address and bit position from a coordinate for 1D tilied (micro
|
||||
* tiled)
|
||||
* @return
|
||||
* The byte address
|
||||
****************************************************************************************************
|
||||
*/
|
||||
UINT_64 EgBasedLib::ComputeFmaskAddrFromCoordMicroTiled(
|
||||
UINT_32 x, ///< [in] x coordinate
|
||||
UINT_32 y, ///< [in] y coordinate
|
||||
UINT_32 slice, ///< [in] slice index
|
||||
UINT_32 sample, ///< [in] sample number
|
||||
UINT_32 plane, ///< [in] plane number
|
||||
UINT_32 pitch, ///< [in] surface pitch in pixels
|
||||
UINT_32 height, ///< [in] surface height in pixels
|
||||
UINT_32 numSamples, ///< [in] number of samples
|
||||
AddrTileMode tileMode, ///< [in] tile mode
|
||||
BOOL_32 resolved, ///< [in] TRUE if this is for resolved fmask
|
||||
UINT_32* pBitPosition ///< [out] pointer to returned bit position
|
||||
) const
|
||||
{
|
||||
UINT_64 addr = 0;
|
||||
UINT_32 effectiveBpp;
|
||||
UINT_32 effectiveSamples;
|
||||
|
||||
//
|
||||
// 2xAA use the same layout as 4xAA
|
||||
//
|
||||
if (numSamples == 2)
|
||||
{
|
||||
numSamples = 4;
|
||||
}
|
||||
|
||||
//
|
||||
// Compute the number of planes.
|
||||
//
|
||||
if (resolved == FALSE)
|
||||
{
|
||||
effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
|
||||
effectiveBpp = numSamples;
|
||||
|
||||
//
|
||||
// Compute the address just like a color surface with numSamples bits per element and
|
||||
// numPlanes samples.
|
||||
//
|
||||
addr = ComputeSurfaceAddrFromCoordMicroTiled(x,
|
||||
y,
|
||||
slice,
|
||||
plane, // sample
|
||||
effectiveBpp,
|
||||
pitch,
|
||||
height,
|
||||
effectiveSamples,
|
||||
tileMode,
|
||||
ADDR_NON_DISPLAYABLE,
|
||||
FALSE,
|
||||
pBitPosition);
|
||||
|
||||
//
|
||||
// Compute the real bit position. Each (sample, plane) is stored with one bit per sample.
|
||||
//
|
||||
|
||||
//
|
||||
// Compute the pixel index with in the micro tile
|
||||
//
|
||||
UINT_32 pixelIndex = ComputePixelIndexWithinMicroTile(x % 8,
|
||||
y % 8,
|
||||
slice,
|
||||
1,
|
||||
tileMode,
|
||||
ADDR_NON_DISPLAYABLE);
|
||||
|
||||
*pBitPosition = ((pixelIndex * numSamples) + sample) & (BITS_PER_BYTE-1);
|
||||
|
||||
UINT_64 bitAddr = BYTES_TO_BITS(addr) + *pBitPosition;
|
||||
|
||||
addr = bitAddr / 8;
|
||||
}
|
||||
else
|
||||
{
|
||||
effectiveBpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
|
||||
effectiveSamples = 1;
|
||||
|
||||
//
|
||||
// Compute the address just like a color surface with numSamples bits per element and
|
||||
// numPlanes samples.
|
||||
//
|
||||
addr = ComputeSurfaceAddrFromCoordMicroTiled(x,
|
||||
y,
|
||||
slice,
|
||||
sample,
|
||||
effectiveBpp,
|
||||
pitch,
|
||||
height,
|
||||
effectiveSamples,
|
||||
tileMode,
|
||||
ADDR_NON_DISPLAYABLE,
|
||||
TRUE,
|
||||
pBitPosition);
|
||||
}
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* EgBasedLib::ComputeFmaskAddrFromCoordMacroTiled
|
||||
*
|
||||
* @brief
|
||||
* Computes the FMASK address and bit position from a coordinate for 2D tilied (macro
|
||||
* tiled)
|
||||
* @return
|
||||
* The byte address
|
||||
****************************************************************************************************
|
||||
*/
|
||||
UINT_64 EgBasedLib::ComputeFmaskAddrFromCoordMacroTiled(
|
||||
UINT_32 x, ///< [in] x coordinate
|
||||
UINT_32 y, ///< [in] y coordinate
|
||||
UINT_32 slice, ///< [in] slice index
|
||||
UINT_32 sample, ///< [in] sample number
|
||||
UINT_32 plane, ///< [in] plane number
|
||||
UINT_32 pitch, ///< [in] surface pitch in pixels
|
||||
UINT_32 height, ///< [in] surface height in pixels
|
||||
UINT_32 numSamples, ///< [in] number of samples
|
||||
AddrTileMode tileMode, ///< [in] tile mode
|
||||
UINT_32 pipeSwizzle, ///< [in] pipe swizzle
|
||||
UINT_32 bankSwizzle, ///< [in] bank swizzle
|
||||
BOOL_32 ignoreSE, ///< [in] TRUE if ignore shader engine
|
||||
ADDR_TILEINFO* pTileInfo, ///< [in] bank structure.**All fields to be valid on entry**
|
||||
BOOL_32 resolved, ///< [in] TRUE if this is for resolved fmask
|
||||
UINT_32* pBitPosition ///< [out] pointer to returned bit position
|
||||
) const
|
||||
{
|
||||
UINT_64 addr = 0;
|
||||
UINT_32 effectiveBpp;
|
||||
UINT_32 effectiveSamples;
|
||||
|
||||
//
|
||||
// 2xAA use the same layout as 4xAA
|
||||
//
|
||||
if (numSamples == 2)
|
||||
{
|
||||
numSamples = 4;
|
||||
}
|
||||
|
||||
//
|
||||
// Compute the number of planes.
|
||||
//
|
||||
if (resolved == FALSE)
|
||||
{
|
||||
effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
|
||||
effectiveBpp = numSamples;
|
||||
|
||||
//
|
||||
// Compute the address just like a color surface with numSamples bits per element and
|
||||
// numPlanes samples.
|
||||
//
|
||||
addr = ComputeSurfaceAddrFromCoordMacroTiled(x,
|
||||
y,
|
||||
slice,
|
||||
plane, // sample
|
||||
effectiveBpp,
|
||||
pitch,
|
||||
height,
|
||||
effectiveSamples,
|
||||
tileMode,
|
||||
ADDR_NON_DISPLAYABLE,// isdisp
|
||||
ignoreSE,// ignore_shader
|
||||
FALSE,// depth_sample_order
|
||||
pipeSwizzle,
|
||||
bankSwizzle,
|
||||
pTileInfo,
|
||||
pBitPosition);
|
||||
|
||||
//
|
||||
// Compute the real bit position. Each (sample, plane) is stored with one bit per sample.
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// Compute the pixel index with in the micro tile
|
||||
//
|
||||
UINT_32 pixelIndex = ComputePixelIndexWithinMicroTile(x ,
|
||||
y ,
|
||||
slice,
|
||||
effectiveBpp,
|
||||
tileMode,
|
||||
ADDR_NON_DISPLAYABLE);
|
||||
|
||||
*pBitPosition = ((pixelIndex * numSamples) + sample) & (BITS_PER_BYTE-1);
|
||||
|
||||
UINT_64 bitAddr = BYTES_TO_BITS(addr) + *pBitPosition;
|
||||
|
||||
addr = bitAddr / 8;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
effectiveBpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
|
||||
effectiveSamples = 1;
|
||||
|
||||
//
|
||||
// Compute the address just like a color surface with numSamples bits per element and
|
||||
// numPlanes samples.
|
||||
//
|
||||
addr = ComputeSurfaceAddrFromCoordMacroTiled(x,
|
||||
y,
|
||||
slice,
|
||||
sample,
|
||||
effectiveBpp,
|
||||
pitch,
|
||||
height,
|
||||
effectiveSamples,
|
||||
tileMode,
|
||||
ADDR_NON_DISPLAYABLE,
|
||||
ignoreSE,
|
||||
TRUE,
|
||||
pipeSwizzle,
|
||||
bankSwizzle,
|
||||
pTileInfo,
|
||||
pBitPosition);
|
||||
}
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* EgBasedLib::ComputeFmaskCoordFromAddrMicroTiled
|
||||
*
|
||||
* @brief
|
||||
* Compute (x,y,slice,sample,plane) coordinates from fmask address
|
||||
* @return
|
||||
* N/A
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
VOID EgBasedLib::ComputeFmaskCoordFromAddrMicroTiled(
|
||||
UINT_64 addr, ///< [in] byte address
|
||||
UINT_32 bitPosition,///< [in] bit position
|
||||
UINT_32 pitch, ///< [in] pitch in pixels
|
||||
UINT_32 height, ///< [in] height in pixels
|
||||
UINT_32 numSamples, ///< [in] number of samples (of color buffer)
|
||||
AddrTileMode tileMode, ///< [in] tile mode
|
||||
BOOL_32 resolved, ///< [in] TRUE if it is resolved fmask
|
||||
UINT_32* pX, ///< [out] X coord
|
||||
UINT_32* pY, ///< [out] Y coord
|
||||
UINT_32* pSlice, ///< [out] slice index
|
||||
UINT_32* pSample, ///< [out] sample index
|
||||
UINT_32* pPlane ///< [out] plane index
|
||||
) const
|
||||
{
|
||||
UINT_32 effectiveBpp;
|
||||
UINT_32 effectiveSamples;
|
||||
|
||||
// 2xAA use the same layout as 4xAA
|
||||
if (numSamples == 2)
|
||||
{
|
||||
numSamples = 4;
|
||||
}
|
||||
|
||||
if (resolved == FALSE)
|
||||
{
|
||||
effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
|
||||
effectiveBpp = numSamples;
|
||||
|
||||
ComputeSurfaceCoordFromAddrMicroTiled(addr,
|
||||
bitPosition,
|
||||
effectiveBpp,
|
||||
pitch,
|
||||
height,
|
||||
effectiveSamples,
|
||||
tileMode,
|
||||
0, // tileBase
|
||||
0, // compBits
|
||||
pX,
|
||||
pY,
|
||||
pSlice,
|
||||
pPlane,
|
||||
ADDR_NON_DISPLAYABLE, // microTileType
|
||||
FALSE // isDepthSampleOrder
|
||||
);
|
||||
|
||||
|
||||
if ( pSample )
|
||||
{
|
||||
*pSample = bitPosition % numSamples;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
effectiveBpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
|
||||
effectiveSamples = 1;
|
||||
|
||||
ComputeSurfaceCoordFromAddrMicroTiled(addr,
|
||||
bitPosition,
|
||||
effectiveBpp,
|
||||
pitch,
|
||||
height,
|
||||
effectiveSamples,
|
||||
tileMode,
|
||||
0, // tileBase
|
||||
0, // compBits
|
||||
pX,
|
||||
pY,
|
||||
pSlice,
|
||||
pSample,
|
||||
ADDR_NON_DISPLAYABLE, // microTileType
|
||||
TRUE // isDepthSampleOrder
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* EgBasedLib::ComputeFmaskCoordFromAddrMacroTiled
|
||||
*
|
||||
* @brief
|
||||
* Compute (x,y,slice,sample,plane) coordinates from
|
||||
* fmask address
|
||||
* @return
|
||||
* N/A
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
VOID EgBasedLib::ComputeFmaskCoordFromAddrMacroTiled(
|
||||
UINT_64 addr, ///< [in] byte address
|
||||
UINT_32 bitPosition,///< [in] bit position
|
||||
UINT_32 pitch, ///< [in] pitch in pixels
|
||||
UINT_32 height, ///< [in] height in pixels
|
||||
UINT_32 numSamples, ///< [in] number of samples (of color buffer)
|
||||
AddrTileMode tileMode, ///< [in] tile mode
|
||||
UINT_32 pipeSwizzle,///< [in] pipe swizzle
|
||||
UINT_32 bankSwizzle,///< [in] bank swizzle
|
||||
BOOL_32 ignoreSE, ///< [in] TRUE if ignore shader engine
|
||||
ADDR_TILEINFO* pTileInfo, ///< [in] bank structure. **All fields to be valid on entry**
|
||||
BOOL_32 resolved, ///< [in] TRUE if it is resolved fmask
|
||||
UINT_32* pX, ///< [out] X coord
|
||||
UINT_32* pY, ///< [out] Y coord
|
||||
UINT_32* pSlice, ///< [out] slice index
|
||||
UINT_32* pSample, ///< [out] sample index
|
||||
UINT_32* pPlane ///< [out] plane index
|
||||
) const
|
||||
{
|
||||
UINT_32 effectiveBpp;
|
||||
UINT_32 effectiveSamples;
|
||||
|
||||
// 2xAA use the same layout as 4xAA
|
||||
if (numSamples == 2)
|
||||
{
|
||||
numSamples = 4;
|
||||
}
|
||||
|
||||
//
|
||||
// Compute the number of planes.
|
||||
//
|
||||
if (resolved == FALSE)
|
||||
{
|
||||
effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
|
||||
effectiveBpp = numSamples;
|
||||
|
||||
ComputeSurfaceCoordFromAddrMacroTiled(addr,
|
||||
bitPosition,
|
||||
effectiveBpp,
|
||||
pitch,
|
||||
height,
|
||||
effectiveSamples,
|
||||
tileMode,
|
||||
0, // No tileBase
|
||||
0, // No compBits
|
||||
ADDR_NON_DISPLAYABLE,
|
||||
ignoreSE,
|
||||
FALSE,
|
||||
pipeSwizzle,
|
||||
bankSwizzle,
|
||||
pTileInfo,
|
||||
pX,
|
||||
pY,
|
||||
pSlice,
|
||||
pPlane);
|
||||
|
||||
if (pSample)
|
||||
{
|
||||
*pSample = bitPosition % numSamples;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
effectiveBpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
|
||||
effectiveSamples = 1;
|
||||
|
||||
ComputeSurfaceCoordFromAddrMacroTiled(addr,
|
||||
bitPosition,
|
||||
effectiveBpp,
|
||||
pitch,
|
||||
height,
|
||||
effectiveSamples,
|
||||
tileMode,
|
||||
0, // No tileBase
|
||||
0, // No compBits
|
||||
ADDR_NON_DISPLAYABLE,
|
||||
ignoreSE,
|
||||
TRUE,
|
||||
pipeSwizzle,
|
||||
bankSwizzle,
|
||||
pTileInfo,
|
||||
pX,
|
||||
pY,
|
||||
pSlice,
|
||||
pSample);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* EgBasedLib::DispatchComputeFmaskCoordFromAddr
|
||||
*
|
||||
* @brief
|
||||
* Compute (x,y,slice,sample,plane) coordinates from
|
||||
* fmask address
|
||||
* @return
|
||||
* N/A
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
VOID EgBasedLib::DispatchComputeFmaskCoordFromAddr(
|
||||
const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, ///< [in] input structure
|
||||
ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut ///< [out] output structure
|
||||
) const
|
||||
{
|
||||
UINT_64 addr = pIn->addr;
|
||||
UINT_32 bitPosition = pIn->bitPosition;
|
||||
UINT_32 pitch = pIn->pitch;
|
||||
UINT_32 height = pIn->height;
|
||||
UINT_32 numSamples = pIn->numSamples;
|
||||
AddrTileMode tileMode = pIn->tileMode;
|
||||
BOOL_32 ignoreSE = pIn->ignoreSE;
|
||||
ADDR_TILEINFO* pTileInfo = pIn->pTileInfo;
|
||||
BOOL_32 resolved = pIn->resolved;
|
||||
|
||||
UINT_32* pX = &pOut->x;
|
||||
UINT_32* pY = &pOut->y;
|
||||
UINT_32* pSlice = &pOut->slice;
|
||||
UINT_32* pSample = &pOut->sample;
|
||||
UINT_32* pPlane = &pOut->plane;
|
||||
|
||||
switch (tileMode)
|
||||
{
|
||||
case ADDR_TM_1D_TILED_THIN1:
|
||||
ComputeFmaskCoordFromAddrMicroTiled(addr,
|
||||
bitPosition,
|
||||
pitch,
|
||||
height,
|
||||
numSamples,
|
||||
tileMode,
|
||||
resolved,
|
||||
pX,
|
||||
pY,
|
||||
pSlice,
|
||||
pSample,
|
||||
pPlane);
|
||||
break;
|
||||
case ADDR_TM_2D_TILED_THIN1://fall through
|
||||
case ADDR_TM_3D_TILED_THIN1:
|
||||
UINT_32 pipeSwizzle;
|
||||
UINT_32 bankSwizzle;
|
||||
|
||||
if (m_configFlags.useCombinedSwizzle)
|
||||
{
|
||||
ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo,
|
||||
&bankSwizzle, &pipeSwizzle);
|
||||
}
|
||||
else
|
||||
{
|
||||
pipeSwizzle = pIn->pipeSwizzle;
|
||||
bankSwizzle = pIn->bankSwizzle;
|
||||
}
|
||||
|
||||
ComputeFmaskCoordFromAddrMacroTiled(addr,
|
||||
bitPosition,
|
||||
pitch,
|
||||
height,
|
||||
numSamples,
|
||||
tileMode,
|
||||
pipeSwizzle,
|
||||
bankSwizzle,
|
||||
ignoreSE,
|
||||
pTileInfo,
|
||||
resolved,
|
||||
pX,
|
||||
pY,
|
||||
pSlice,
|
||||
pSample,
|
||||
pPlane);
|
||||
break;
|
||||
default:
|
||||
ADDR_ASSERT_ALWAYS();
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* EgBasedLib::ComputeFmaskNumPlanesFromNumSamples
|
||||
|
|
|
@ -32,16 +32,9 @@
|
|||
*/
|
||||
|
||||
#include "siaddrlib.h"
|
||||
|
||||
#include "si_gb_reg.h"
|
||||
|
||||
#include "si_ci_vi_merged_enum.h"
|
||||
|
||||
#if BRAHMA_BUILD
|
||||
#include "amdgpu_id.h"
|
||||
#else
|
||||
#include "si_id.h"
|
||||
#endif
|
||||
#include "amdgpu_asic_addr.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
@ -2664,7 +2657,8 @@ ADDR_E_RETURNCODE SiLib::HwlComputeSurfaceInfo(
|
|||
|
||||
if ((pIn->numSlices > 1) &&
|
||||
(IsMacroTiled(pOut->tileMode) == TRUE) &&
|
||||
(m_chipFamily == ADDR_CHIP_FAMILY_SI))
|
||||
((m_chipFamily == ADDR_CHIP_FAMILY_SI) ||
|
||||
(IsPrtTileMode(pOut->tileMode) == FALSE)))
|
||||
{
|
||||
pOut->equationIndex = ADDR_INVALID_EQUATION_INDEX;
|
||||
}
|
||||
|
@ -2822,8 +2816,8 @@ VOID SiLib::HwlCheckLastMacroTiledLvl(
|
|||
****************************************************************************************************
|
||||
*/
|
||||
AddrTileMode SiLib::HwlDegradeThickTileMode(
|
||||
AddrTileMode baseTileMode, ///< [in] base tile mode
|
||||
UINT_32 numSlices, ///< [in] current number of slices
|
||||
AddrTileMode baseTileMode, ///< base tile mode
|
||||
UINT_32 numSlices, ///< current number of slices
|
||||
UINT_32* pBytesPerTile ///< [in,out] pointer to bytes per slice
|
||||
) const
|
||||
{
|
||||
|
@ -2963,9 +2957,9 @@ INT_32 SiLib::HwlPostCheckTileIndex(
|
|||
****************************************************************************************************
|
||||
*/
|
||||
ADDR_E_RETURNCODE SiLib::HwlSetupTileCfg(
|
||||
UINT_32 bpp, ///< [in] Bits per pixel
|
||||
INT_32 index, ///< [in] Tile index
|
||||
INT_32 macroModeIndex, ///< [in] Index in macro tile mode table(CI)
|
||||
UINT_32 bpp, ///< Bits per pixel
|
||||
INT_32 index, ///< Tile index
|
||||
INT_32 macroModeIndex, ///< Index in macro tile mode table(CI)
|
||||
ADDR_TILEINFO* pInfo, ///< [out] Tile Info
|
||||
AddrTileMode* pMode, ///< [out] Tile mode
|
||||
AddrTileType* pType ///< [out] Tile type
|
||||
|
|
|
@ -59,18 +59,36 @@ struct TileConfig
|
|||
* @brief SI specific settings structure.
|
||||
****************************************************************************************************
|
||||
*/
|
||||
struct SIChipSettings
|
||||
struct SiChipSettings
|
||||
{
|
||||
struct
|
||||
{
|
||||
UINT_32 isSouthernIsland : 1;
|
||||
UINT_32 isTahiti : 1;
|
||||
UINT_32 isPitCairn : 1;
|
||||
UINT_32 isCapeVerde : 1;
|
||||
/// Oland/Hainan are of GFXIP 6.0, similar with SI
|
||||
UINT_32 isOland : 1;
|
||||
UINT_32 isHainan : 1;
|
||||
};
|
||||
UINT_32 isSouthernIsland : 1;
|
||||
UINT_32 isTahiti : 1;
|
||||
UINT_32 isPitCairn : 1;
|
||||
UINT_32 isCapeVerde : 1;
|
||||
// Oland/Hainan are of GFXIP 6.0, similar with SI
|
||||
UINT_32 isOland : 1;
|
||||
UINT_32 isHainan : 1;
|
||||
|
||||
// CI
|
||||
UINT_32 isSeaIsland : 1;
|
||||
UINT_32 isBonaire : 1;
|
||||
UINT_32 isKaveri : 1;
|
||||
UINT_32 isSpectre : 1;
|
||||
UINT_32 isSpooky : 1;
|
||||
UINT_32 isKalindi : 1;
|
||||
// Hawaii is GFXIP 7.2
|
||||
UINT_32 isHawaii : 1;
|
||||
|
||||
// VI
|
||||
UINT_32 isVolcanicIslands : 1;
|
||||
UINT_32 isIceland : 1;
|
||||
UINT_32 isTonga : 1;
|
||||
UINT_32 isFiji : 1;
|
||||
UINT_32 isPolaris10 : 1;
|
||||
UINT_32 isPolaris11 : 1;
|
||||
UINT_32 isPolaris12 : 1;
|
||||
// VI fusion
|
||||
UINT_32 isCarrizo : 1;
|
||||
};
|
||||
|
||||
/**
|
||||
|
@ -312,12 +330,12 @@ protected:
|
|||
|
||||
UINT_32 m_uncompressDepthEqIndex;
|
||||
|
||||
SiChipSettings m_settings;
|
||||
|
||||
private:
|
||||
|
||||
VOID ReadGbTileMode(UINT_32 regValue, TileConfig* pCfg) const;
|
||||
BOOL_32 InitTileSettingTable(const UINT_32 *pSetting, UINT_32 noOfEntries);
|
||||
|
||||
SIChipSettings m_settings;
|
||||
};
|
||||
|
||||
} // V1
|
||||
|
|
|
@ -27,7 +27,7 @@
|
|||
|
||||
#include "ac_surface.h"
|
||||
#include "amd_family.h"
|
||||
#include "amdgpu_id.h"
|
||||
#include "addrlib/amdgpu_asic_addr.h"
|
||||
#include "ac_gpu_info.h"
|
||||
#include "util/macros.h"
|
||||
#include "util/u_atomic.h"
|
||||
|
@ -49,90 +49,95 @@
|
|||
#define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
|
||||
#endif
|
||||
|
||||
static unsigned get_first(unsigned x, unsigned y)
|
||||
{
|
||||
return x;
|
||||
}
|
||||
|
||||
static void addrlib_family_rev_id(enum radeon_family family,
|
||||
unsigned *addrlib_family,
|
||||
unsigned *addrlib_revid)
|
||||
unsigned *addrlib_family,
|
||||
unsigned *addrlib_revid)
|
||||
{
|
||||
switch (family) {
|
||||
case CHIP_TAHITI:
|
||||
*addrlib_family = FAMILY_SI;
|
||||
*addrlib_revid = SI_TAHITI_P_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_TAHITI_RANGE);
|
||||
break;
|
||||
case CHIP_PITCAIRN:
|
||||
*addrlib_family = FAMILY_SI;
|
||||
*addrlib_revid = SI_PITCAIRN_PM_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_PITCAIRN_RANGE);
|
||||
break;
|
||||
case CHIP_VERDE:
|
||||
*addrlib_family = FAMILY_SI;
|
||||
*addrlib_revid = SI_CAPEVERDE_M_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_CAPEVERDE_RANGE);
|
||||
break;
|
||||
case CHIP_OLAND:
|
||||
*addrlib_family = FAMILY_SI;
|
||||
*addrlib_revid = SI_OLAND_M_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_OLAND_RANGE);
|
||||
break;
|
||||
case CHIP_HAINAN:
|
||||
*addrlib_family = FAMILY_SI;
|
||||
*addrlib_revid = SI_HAINAN_V_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_HAINAN_RANGE);
|
||||
break;
|
||||
case CHIP_BONAIRE:
|
||||
*addrlib_family = FAMILY_CI;
|
||||
*addrlib_revid = CI_BONAIRE_M_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_BONAIRE_RANGE);
|
||||
break;
|
||||
case CHIP_KAVERI:
|
||||
*addrlib_family = FAMILY_KV;
|
||||
*addrlib_revid = KV_SPECTRE_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_SPECTRE_RANGE);
|
||||
break;
|
||||
case CHIP_KABINI:
|
||||
*addrlib_family = FAMILY_KV;
|
||||
*addrlib_revid = KB_KALINDI_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_KALINDI_RANGE);
|
||||
break;
|
||||
case CHIP_HAWAII:
|
||||
*addrlib_family = FAMILY_CI;
|
||||
*addrlib_revid = CI_HAWAII_P_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_HAWAII_RANGE);
|
||||
break;
|
||||
case CHIP_MULLINS:
|
||||
*addrlib_family = FAMILY_KV;
|
||||
*addrlib_revid = ML_GODAVARI_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_GODAVARI_RANGE);
|
||||
break;
|
||||
case CHIP_TONGA:
|
||||
*addrlib_family = FAMILY_VI;
|
||||
*addrlib_revid = VI_TONGA_P_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_TONGA_RANGE);
|
||||
break;
|
||||
case CHIP_ICELAND:
|
||||
*addrlib_family = FAMILY_VI;
|
||||
*addrlib_revid = VI_ICELAND_M_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_ICELAND_RANGE);
|
||||
break;
|
||||
case CHIP_CARRIZO:
|
||||
*addrlib_family = FAMILY_CZ;
|
||||
*addrlib_revid = CARRIZO_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_CARRIZO_RANGE);
|
||||
break;
|
||||
case CHIP_STONEY:
|
||||
*addrlib_family = FAMILY_CZ;
|
||||
*addrlib_revid = STONEY_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_STONEY_RANGE);
|
||||
break;
|
||||
case CHIP_FIJI:
|
||||
*addrlib_family = FAMILY_VI;
|
||||
*addrlib_revid = VI_FIJI_P_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_FIJI_RANGE);
|
||||
break;
|
||||
case CHIP_POLARIS10:
|
||||
*addrlib_family = FAMILY_VI;
|
||||
*addrlib_revid = VI_POLARIS10_P_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_POLARIS10_RANGE);
|
||||
break;
|
||||
case CHIP_POLARIS11:
|
||||
*addrlib_family = FAMILY_VI;
|
||||
*addrlib_revid = VI_POLARIS11_M_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_POLARIS11_RANGE);
|
||||
break;
|
||||
case CHIP_POLARIS12:
|
||||
*addrlib_family = FAMILY_VI;
|
||||
*addrlib_revid = VI_POLARIS12_V_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_POLARIS12_RANGE);
|
||||
break;
|
||||
case CHIP_VEGA10:
|
||||
*addrlib_family = FAMILY_AI;
|
||||
*addrlib_revid = AI_VEGA10_P_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
|
||||
break;
|
||||
case CHIP_RAVEN:
|
||||
*addrlib_family = FAMILY_RV;
|
||||
*addrlib_revid = RAVEN_A0;
|
||||
*addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
|
||||
break;
|
||||
default:
|
||||
fprintf(stderr, "amdgpu: Unknown family.\n");
|
||||
|
@ -167,7 +172,7 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
|
|||
regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
|
||||
createFlags.value = 0;
|
||||
|
||||
addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
|
||||
addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
|
||||
if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
|
||||
return NULL;
|
||||
|
||||
|
|
|
@ -1,198 +0,0 @@
|
|||
/*
|
||||
* Copyright © 2014 Advanced Micro Devices, Inc.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sub license, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
|
||||
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||||
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial portions
|
||||
* of the Software.
|
||||
*/
|
||||
|
||||
/**
|
||||
* This file is included by addrlib. It adds GPU family definitions and
|
||||
* macros compatible with addrlib.
|
||||
*/
|
||||
|
||||
#ifndef AMDGPU_ID_H
|
||||
#define AMDGPU_ID_H
|
||||
|
||||
#include "util/u_endian.h"
|
||||
|
||||
#if defined(PIPE_ARCH_LITTLE_ENDIAN)
|
||||
#define LITTLEENDIAN_CPU
|
||||
#elif defined(PIPE_ARCH_BIG_ENDIAN)
|
||||
#define BIGENDIAN_CPU
|
||||
#endif
|
||||
|
||||
enum {
|
||||
FAMILY_UNKNOWN,
|
||||
FAMILY_SI,
|
||||
FAMILY_CI,
|
||||
FAMILY_KV,
|
||||
FAMILY_VI,
|
||||
FAMILY_CZ,
|
||||
FAMILY_PI,
|
||||
FAMILY_AI,
|
||||
FAMILY_RV,
|
||||
FAMILY_LAST,
|
||||
};
|
||||
|
||||
/* SI specific rev IDs */
|
||||
enum {
|
||||
SI_TAHITI_P_A11 = 1,
|
||||
SI_TAHITI_P_A0 = SI_TAHITI_P_A11, /*A0 is alias of A11*/
|
||||
SI_TAHITI_P_A21 = 5,
|
||||
SI_TAHITI_P_B0 = SI_TAHITI_P_A21, /*B0 is alias of A21*/
|
||||
SI_TAHITI_P_A22 = 6,
|
||||
SI_TAHITI_P_B1 = SI_TAHITI_P_A22, /*B1 is alias of A22*/
|
||||
|
||||
SI_PITCAIRN_PM_A11 = 20,
|
||||
SI_PITCAIRN_PM_A0 = SI_PITCAIRN_PM_A11, /*A0 is alias of A11*/
|
||||
SI_PITCAIRN_PM_A12 = 21,
|
||||
SI_PITCAIRN_PM_A1 = SI_PITCAIRN_PM_A12, /*A1 is alias of A12*/
|
||||
|
||||
SI_CAPEVERDE_M_A11 = 40,
|
||||
SI_CAPEVERDE_M_A0 = SI_CAPEVERDE_M_A11, /*A0 is alias of A11*/
|
||||
SI_CAPEVERDE_M_A12 = 41,
|
||||
SI_CAPEVERDE_M_A1 = SI_CAPEVERDE_M_A12, /*A1 is alias of A12*/
|
||||
|
||||
SI_OLAND_M_A0 = 60,
|
||||
|
||||
SI_HAINAN_V_A0 = 70,
|
||||
|
||||
SI_UNKNOWN = 0xFF
|
||||
};
|
||||
|
||||
|
||||
#define ASICREV_IS_TAHITI_P(eChipRev) \
|
||||
(eChipRev < SI_PITCAIRN_PM_A11)
|
||||
#define ASICREV_IS_PITCAIRN_PM(eChipRev) \
|
||||
((eChipRev >= SI_PITCAIRN_PM_A11) && (eChipRev < SI_CAPEVERDE_M_A11))
|
||||
#define ASICREV_IS_CAPEVERDE_M(eChipRev) \
|
||||
((eChipRev >= SI_CAPEVERDE_M_A11) && (eChipRev < SI_OLAND_M_A0))
|
||||
#define ASICREV_IS_OLAND_M(eChipRev) \
|
||||
((eChipRev >= SI_OLAND_M_A0) && (eChipRev < SI_HAINAN_V_A0))
|
||||
#define ASICREV_IS_HAINAN_V(eChipRev) \
|
||||
(eChipRev >= SI_HAINAN_V_A0)
|
||||
|
||||
/* CI specific revIDs */
|
||||
enum {
|
||||
CI_BONAIRE_M_A0 = 20,
|
||||
CI_BONAIRE_M_A1 = 21,
|
||||
|
||||
CI_HAWAII_P_A0 = 40,
|
||||
|
||||
CI_UNKNOWN = 0xFF
|
||||
};
|
||||
|
||||
#define ASICREV_IS_BONAIRE_M(eChipRev) \
|
||||
((eChipRev >= CI_BONAIRE_M_A0) && (eChipRev < CI_HAWAII_P_A0))
|
||||
#define ASICREV_IS_HAWAII_P(eChipRev) \
|
||||
(eChipRev >= CI_HAWAII_P_A0)
|
||||
|
||||
/* KV specific rev IDs */
|
||||
enum {
|
||||
KV_SPECTRE_A0 = 0x01, /* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
|
||||
KV_SPOOKY_A0 = 0x41, /* KV2 with Spooky GFX core, including downgraded from Spectre core, 3-4-1-1 (CU-Pix-Primitive-RB) */
|
||||
KB_KALINDI_A0 = 0x81, /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
|
||||
KB_KALINDI_A1 = 0x82, /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
|
||||
BV_KALINDI_A2 = 0x85, /* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
|
||||
ML_GODAVARI_A0 = 0xa1, /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
|
||||
ML_GODAVARI_A1 = 0xa2, /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
|
||||
KV_UNKNOWN = 0xFF
|
||||
};
|
||||
|
||||
#define ASICREV_IS_SPECTRE(eChipRev) \
|
||||
((eChipRev >= KV_SPECTRE_A0) && (eChipRev < KV_SPOOKY_A0)) /* identify all versions of SPRECTRE and supported features set */
|
||||
#define ASICREV_IS_SPOOKY(eChipRev) \
|
||||
((eChipRev >= KV_SPOOKY_A0) && (eChipRev < KB_KALINDI_A0)) /* identify all versions of SPOOKY and supported features set */
|
||||
#define ASICREV_IS_KALINDI(eChipRev) \
|
||||
((eChipRev >= KB_KALINDI_A0) && (eChipRev < KV_UNKNOWN)) /* identify all versions of KALINDI and supported features set */
|
||||
|
||||
/* Following macros are subset of ASICREV_IS_KALINDI macro */
|
||||
#define ASICREV_IS_KALINDI_BHAVANI(eChipRev) \
|
||||
((eChipRev >= BV_KALINDI_A2) && (eChipRev < ML_GODAVARI_A0)) /* identify all versions of BHAVANI and supported features set */
|
||||
#define ASICREV_IS_KALINDI_GODAVARI(eChipRev) \
|
||||
((eChipRev >= ML_GODAVARI_A0) && (eChipRev < KV_UNKNOWN)) /* identify all versions of GODAVARI and supported features set */
|
||||
|
||||
/* VI specific rev IDs */
|
||||
enum {
|
||||
VI_ICELAND_M_A0 = 1,
|
||||
|
||||
VI_TONGA_P_A0 = 20,
|
||||
VI_TONGA_P_A1 = 21,
|
||||
|
||||
VI_FIJI_P_A0 = 60,
|
||||
|
||||
VI_POLARIS10_P_A0 = 80,
|
||||
|
||||
VI_POLARIS11_M_A0 = 90,
|
||||
|
||||
VI_POLARIS12_V_A0 = 100,
|
||||
|
||||
VI_UNKNOWN = 0xFF
|
||||
};
|
||||
|
||||
|
||||
#define ASICREV_IS_ICELAND_M(eChipRev) \
|
||||
(eChipRev < VI_TONGA_P_A0)
|
||||
#define ASICREV_IS_TONGA_P(eChipRev) \
|
||||
((eChipRev >= VI_TONGA_P_A0) && (eChipRev < VI_FIJI_P_A0))
|
||||
#define ASICREV_IS_FIJI_P(eChipRev) \
|
||||
((eChipRev >= VI_FIJI_P_A0) && (eChipRev < VI_POLARIS10_P_A0))
|
||||
#define ASICREV_IS_POLARIS10_P(eChipRev)\
|
||||
((eChipRev >= VI_POLARIS10_P_A0) && (eChipRev < VI_POLARIS11_M_A0))
|
||||
#define ASICREV_IS_POLARIS11_M(eChipRev) \
|
||||
(eChipRev >= VI_POLARIS11_M_A0 && eChipRev < VI_POLARIS12_V_A0)
|
||||
#define ASICREV_IS_POLARIS12_V(eChipRev)\
|
||||
(eChipRev >= VI_POLARIS12_V_A0)
|
||||
|
||||
/* CZ specific rev IDs */
|
||||
enum {
|
||||
CARRIZO_A0 = 0x01,
|
||||
STONEY_A0 = 0x61,
|
||||
CZ_UNKNOWN = 0xFF
|
||||
};
|
||||
|
||||
#define ASICREV_IS_CARRIZO(eChipRev) \
|
||||
((eChipRev >= CARRIZO_A0) && (eChipRev < STONEY_A0))
|
||||
|
||||
#define ASICREV_IS_STONEY(eChipRev) \
|
||||
((eChipRev >= STONEY_A0) && (eChipRev < CZ_UNKNOWN))
|
||||
|
||||
/* AI specific rev IDs */
|
||||
enum {
|
||||
AI_VEGA10_P_A0 = 0x01,
|
||||
|
||||
AI_UNKNOWN = 0xFF
|
||||
};
|
||||
|
||||
#define ASICREV_IS_VEGA10_P(eChipRev) \
|
||||
((eChipRev) >= AI_VEGA10_P_A0 && (eChipRev) < AI_UNKNOWN)
|
||||
|
||||
/* RV specific rev IDs */
|
||||
enum {
|
||||
RAVEN_A0 = 0x01,
|
||||
RAVEN_UNKNOWN = 0xFF
|
||||
};
|
||||
|
||||
#define ASICREV_IS_RAVEN(eChipRev) \
|
||||
((eChipRev) >= RAVEN_A0 && (eChipRev) < RAVEN_UNKNOWN)
|
||||
|
||||
#endif /* AMDGPU_ID_H */
|
|
@ -39,7 +39,6 @@
|
|||
#include <xf86drm.h>
|
||||
#include <amdgpu.h>
|
||||
#include <amdgpu_drm.h>
|
||||
#include "amdgpu_id.h"
|
||||
#include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
|
||||
#include "ac_llvm_util.h"
|
||||
#include "vk_format.h"
|
||||
|
|
|
@ -28,7 +28,6 @@
|
|||
#include <assert.h>
|
||||
|
||||
#include "ac_debug.h"
|
||||
#include "amdgpu_id.h"
|
||||
#include "radv_radeon_winsys.h"
|
||||
#include "radv_amdgpu_cs.h"
|
||||
#include "radv_amdgpu_bo.h"
|
||||
|
|
|
@ -28,7 +28,6 @@
|
|||
#include "radv_amdgpu_winsys_public.h"
|
||||
#include "radv_amdgpu_surface.h"
|
||||
#include "radv_debug.h"
|
||||
#include "amdgpu_id.h"
|
||||
#include "ac_surface.h"
|
||||
#include "xf86drm.h"
|
||||
#include <stdio.h>
|
||||
|
|
|
@ -35,7 +35,6 @@
|
|||
#include <xf86drm.h>
|
||||
#include <stdio.h>
|
||||
#include <sys/stat.h>
|
||||
#include "amd/common/amdgpu_id.h"
|
||||
#include "amd/common/sid.h"
|
||||
#include "amd/common/gfx9d.h"
|
||||
|
||||
|
|
Loading…
Reference in New Issue