i965: Fix the response len of masked sampler messages for 8-wide dispatch.
The bad response length would hang the GPU with a masked sample in a shader using control flow. For 8-wide, the response length is always 4, and masked slots are just not written to. brw_wm_glsl.c already allocates registers in the right locations. Fixes piglit glsl-fs-bug25902 (fd.o bug #25902). (cherry picked from commitf6d210c284
) (cherry picked from commitdc8c035944
)
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@ -1290,7 +1290,7 @@ void brw_SAMPLE(struct brw_compile *p,
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GLuint simd_mode)
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GLuint simd_mode)
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{
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{
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GLboolean need_stall = 0;
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GLboolean need_stall = 0;
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if (writemask == 0) {
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if (writemask == 0) {
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/*printf("%s: zero writemask??\n", __FUNCTION__); */
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/*printf("%s: zero writemask??\n", __FUNCTION__); */
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return;
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return;
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@ -1327,8 +1327,14 @@ void brw_SAMPLE(struct brw_compile *p,
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/* printf("need stall %x %x\n", newmask , writemask); */
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/* printf("need stall %x %x\n", newmask , writemask); */
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}
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}
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else {
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else {
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GLboolean dispatch_16 = GL_FALSE;
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struct brw_reg m1 = brw_message_reg(msg_reg_nr);
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struct brw_reg m1 = brw_message_reg(msg_reg_nr);
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guess_execution_size(p->current, dest);
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if (p->current->header.execution_size == BRW_EXECUTE_16)
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dispatch_16 = GL_TRUE;
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newmask = ~newmask & WRITEMASK_XYZW;
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newmask = ~newmask & WRITEMASK_XYZW;
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brw_push_insn_state(p);
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brw_push_insn_state(p);
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@ -1343,7 +1349,13 @@ void brw_SAMPLE(struct brw_compile *p,
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src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW);
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src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW);
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dest = offset(dest, dst_offset);
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dest = offset(dest, dst_offset);
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response_length = len * 2;
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/* For 16-wide dispatch, masked channels are skipped in the
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* response. For 8-wide, masked channels still take up slots,
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* and are just not written to.
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*/
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if (dispatch_16)
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response_length = len * 2;
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}
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}
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}
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}
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