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i965: Fix the response len of masked sampler messages for 8-wide dispatch. 

The bad response length would hang the GPU with a masked sample in a
shader using control flow.  For 8-wide, the response length is always
4, and masked slots are just not written to.  brw_wm_glsl.c already
allocates registers in the right locations.

Fixes piglit glsl-fs-bug25902 (fd.o bug #25902).
(cherry picked from commit f6d210c284)
(cherry picked from commit dc8c035944)
This commit is contained in:
Eric Anholt 2010-03-10 10:38:20 -08:00
parent c1c9fad293
commit 7ee4db50b1
1 changed files with 15 additions and 3 deletions
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18
src/mesa/drivers/dri/i965/brw_eu_emit.c
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@ -1290,7 +1290,7 @@ void brw_SAMPLE(struct brw_compile *p,
GLuint simd_mode)
{
GLboolean need_stall = 0;
if (writemask == 0) {
/*printf("%s: zero writemask??\n", __FUNCTION__); */
return;
@ -1327,8 +1327,14 @@ void brw_SAMPLE(struct brw_compile *p,
/* printf("need stall %x %x\n", newmask , writemask); */
}
else {
GLboolean dispatch_16 = GL_FALSE;
struct brw_reg m1 = brw_message_reg(msg_reg_nr);
guess_execution_size(p->current, dest);
if (p->current->header.execution_size == BRW_EXECUTE_16)
dispatch_16 = GL_TRUE;
newmask = ~newmask & WRITEMASK_XYZW;
brw_push_insn_state(p);
@ -1343,7 +1349,13 @@ void brw_SAMPLE(struct brw_compile *p,
src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW);
dest = offset(dest, dst_offset);
response_length = len * 2;
/* For 16-wide dispatch, masked channels are skipped in the
* response. For 8-wide, masked channels still take up slots,
* and are just not written to.
*/
if (dispatch_16)
response_length = len * 2;
}
}