radeonsi: optimize si_invalidate_buffer based on bind_history
Just enclose each section with: if (rbuffer->bind_history & PIPE_BIND_...) Bioshock Infinite: +1% performance Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
This commit is contained in:
Marek Olšák
parent
e43bd861e8
commit
7e6428e0a8
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@ -1503,114 +1503,127 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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*/
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/* Vertex buffers. */
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for (i = 0; i < num_elems; i++) {
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int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
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if (rbuffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
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for (i = 0; i < num_elems; i++) {
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int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
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if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
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continue;
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if (!sctx->vertex_buffer[vb].buffer)
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continue;
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if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
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continue;
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if (!sctx->vertex_buffer[vb].buffer)
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continue;
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if (sctx->vertex_buffer[vb].buffer == buf) {
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sctx->vertex_buffers_dirty = true;
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break;
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if (sctx->vertex_buffer[vb].buffer == buf) {
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sctx->vertex_buffers_dirty = true;
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break;
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}
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}
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}
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/* Streamout buffers. (other internal buffers can't be invalidated) */
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for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
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struct si_buffer_resources *buffers = &sctx->rw_buffers;
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struct si_descriptors *descs =
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&sctx->descriptors[SI_DESCS_RW_BUFFERS];
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if (rbuffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
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for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
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struct si_buffer_resources *buffers = &sctx->rw_buffers;
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struct si_descriptors *descs =
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&sctx->descriptors[SI_DESCS_RW_BUFFERS];
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if (buffers->buffers[i] != buf)
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continue;
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if (buffers->buffers[i] != buf)
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continue;
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si_desc_reset_buffer_offset(ctx, descs->list + i*4,
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old_va, buf);
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descs->dirty_mask |= 1u << i;
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sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
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si_desc_reset_buffer_offset(ctx, descs->list + i*4,
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old_va, buf);
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descs->dirty_mask |= 1u << i;
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sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
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radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
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rbuffer, buffers->shader_usage,
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RADEON_PRIO_SHADER_RW_BUFFER,
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true);
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radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
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rbuffer, buffers->shader_usage,
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RADEON_PRIO_SHADER_RW_BUFFER,
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true);
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/* Update the streamout state. */
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if (sctx->b.streamout.begin_emitted)
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r600_emit_streamout_end(&sctx->b);
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sctx->b.streamout.append_bitmask =
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sctx->b.streamout.enabled_mask;
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r600_streamout_buffers_dirty(&sctx->b);
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/* Update the streamout state. */
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if (sctx->b.streamout.begin_emitted)
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r600_emit_streamout_end(&sctx->b);
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sctx->b.streamout.append_bitmask =
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sctx->b.streamout.enabled_mask;
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r600_streamout_buffers_dirty(&sctx->b);
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}
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}
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/* Constant and shader buffers. */
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for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
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si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
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si_const_buffer_descriptors_idx(shader),
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buf, old_va);
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si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
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si_shader_buffer_descriptors_idx(shader),
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buf, old_va);
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if (rbuffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
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for (shader = 0; shader < SI_NUM_SHADERS; shader++)
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si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
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si_const_buffer_descriptors_idx(shader),
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buf, old_va);
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}
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/* Texture buffers - update virtual addresses in sampler view descriptors. */
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LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
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if (view->base.texture == buf) {
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si_desc_reset_buffer_offset(ctx, &view->state[4], old_va, buf);
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if (rbuffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
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for (shader = 0; shader < SI_NUM_SHADERS; shader++)
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si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
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si_shader_buffer_descriptors_idx(shader),
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buf, old_va);
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}
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if (rbuffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
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/* Texture buffers - update virtual addresses in sampler view descriptors. */
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LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
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if (view->base.texture == buf) {
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si_desc_reset_buffer_offset(ctx, &view->state[4], old_va, buf);
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}
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}
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}
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/* Texture buffers - update bindings. */
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for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
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struct si_sampler_views *views = &sctx->samplers[shader].views;
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struct si_descriptors *descs =
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si_sampler_descriptors(sctx, shader);
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unsigned mask = views->enabled_mask;
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/* Texture buffers - update bindings. */
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for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
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struct si_sampler_views *views = &sctx->samplers[shader].views;
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struct si_descriptors *descs =
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si_sampler_descriptors(sctx, shader);
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unsigned mask = views->enabled_mask;
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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if (views->views[i]->texture == buf) {
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si_desc_reset_buffer_offset(ctx,
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descs->list +
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i * 16 + 4,
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old_va, buf);
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descs->dirty_mask |= 1u << i;
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sctx->descriptors_dirty |=
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1u << si_sampler_descriptors_idx(shader);
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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if (views->views[i]->texture == buf) {
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si_desc_reset_buffer_offset(ctx,
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descs->list +
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i * 16 + 4,
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old_va, buf);
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descs->dirty_mask |= 1u << i;
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sctx->descriptors_dirty |=
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1u << si_sampler_descriptors_idx(shader);
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radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
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rbuffer, RADEON_USAGE_READ,
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RADEON_PRIO_SAMPLER_BUFFER,
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true);
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radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
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rbuffer, RADEON_USAGE_READ,
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RADEON_PRIO_SAMPLER_BUFFER,
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true);
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}
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}
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}
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}
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/* Shader images */
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for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
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struct si_images_info *images = &sctx->images[shader];
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struct si_descriptors *descs =
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si_image_descriptors(sctx, shader);
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unsigned mask = images->enabled_mask;
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if (rbuffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
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for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
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struct si_images_info *images = &sctx->images[shader];
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struct si_descriptors *descs =
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si_image_descriptors(sctx, shader);
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unsigned mask = images->enabled_mask;
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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if (images->views[i].resource == buf) {
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if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
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si_mark_image_range_valid(&images->views[i]);
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if (images->views[i].resource == buf) {
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if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
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si_mark_image_range_valid(&images->views[i]);
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si_desc_reset_buffer_offset(
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ctx, descs->list + i * 8 + 4,
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old_va, buf);
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descs->dirty_mask |= 1u << i;
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sctx->descriptors_dirty |=
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1u << si_image_descriptors_idx(shader);
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si_desc_reset_buffer_offset(
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ctx, descs->list + i * 8 + 4,
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old_va, buf);
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descs->dirty_mask |= 1u << i;
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sctx->descriptors_dirty |=
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1u << si_image_descriptors_idx(shader);
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radeon_add_to_buffer_list_check_mem(
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&sctx->b, &sctx->b.gfx, rbuffer,
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RADEON_USAGE_READWRITE,
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RADEON_PRIO_SAMPLER_BUFFER, true);
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radeon_add_to_buffer_list_check_mem(
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&sctx->b, &sctx->b.gfx, rbuffer,
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RADEON_USAGE_READWRITE,
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RADEON_PRIO_SAMPLER_BUFFER, true);
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}
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}
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}
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}
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