amd/registers: add some SQ_WAVE_* register definitions
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
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Samuel Pitoiset
Marge Bot
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3aa71a61dd
commit
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@ -1487,6 +1487,19 @@
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{"name": "RE_Z", "value": 2},
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{"name": "EARLY_Z_THEN_RE_Z", "value": 3}
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]
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},
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"ExcpEn": {
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"entries": [
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{"name": "INVALID", "value": 1},
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{"name": "INPUT_DENORMAL", "value": 2},
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{"name": "DIVIDE_BY_ZERO", "value": 4},
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{"name": "OVERFLOW", "value": 8},
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{"name": "UNDERFLOW", "value": 16},
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{"name": "INEXACT", "value": 32},
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{"name": "INT_DIVIDE_BY_ZERO", "value": 64},
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{"name": "ADDRESS_WATCH", "value": 128},
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{"name": "MEMORY_VIOLATION", "value": 256}
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]
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}
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},
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"register_mappings": [
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@ -11457,6 +11470,42 @@
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"map": {"at": 198988, "to": "mm"},
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"name": "WD_POS_BUF_BASE_HI",
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"type_ref": "VGT_TF_MEMORY_BASE_HI"
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},
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{
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"chips": ["gfx8"],
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"map": {"at": 2, "to": "hw"},
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"name": "SQ_HW_REG_STATUS",
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"type_ref": "SQ_WAVE_STATUS_vi"
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},
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{
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"chips": ["gfx8"],
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"map": {"at": 3, "to": "hw"},
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"name": "SQ_HW_REG_TRAP_STS",
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"type_ref": "SQ_WAVE_TRAP_STS"
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},
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{
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"chips": ["gfx8"],
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"map": {"at": 4, "to": "hw"},
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"name": "SQ_HW_REG_HW_ID",
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"type_ref": "SQ_WAVE_HW_ID_cik_vi"
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},
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{
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"chips": ["gfx8"],
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"map": {"at": 5, "to": "hw"},
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"name": "SQ_HW_REG_GPR_ALLOC",
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"type_ref": "SQ_WAVE_GPR_ALLOC"
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},
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{
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"chips": ["gfx8"],
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"map": {"at": 6, "to": "hw"},
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"name": "SQ_HW_REG_LDS_ALLOC",
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"type_ref": "SQ_WAVE_LDS_ALLOC"
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},
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{
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"chips": ["gfx8"],
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"map": {"at": 7, "to": "hw"},
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"name": "SQ_HW_REG_IB_STS",
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"type_ref": "SQ_WAVE_IB_STS_cik_vi"
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}
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],
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"register_types": {
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@ -16048,6 +16097,80 @@
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{"bits": [0, 7], "name": "PERF_SEL"},
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{"bits": [28, 31], "name": "PERF_MODE"}
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]
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},
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"SQ_WAVE_GPR_ALLOC": {
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"fields": [
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{"bits": [0, 5], "name": "VGPR_BASE"},
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{"bits": [8, 13], "name": "VGPR_SIZE"},
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{"bits": [16, 21], "name": "SGPR_BASE"},
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{"bits": [24, 27], "name": "SGPR_SIZE"}
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]
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},
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"SQ_WAVE_LDS_ALLOC": {
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"fields": [
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{"bits": [0, 7], "name": "LDS_BASE"},
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{"bits": [12, 20], "name": "LDS_SIZE"}
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]
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},
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"SQ_WAVE_TRAP_STS": {
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"fields": [
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{"bits": [0, 8], "enum_ref": "ExcpEn", "name": "EXCP"},
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{"bits": [10, 10], "name": "SAVE_CTX_vi"},
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{"bits": [16, 21], "name": "EXCP_CYCLE"},
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{"bits": [29, 31], "name": "DP_RATE"}
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]
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},
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"SQ_WAVE_STATUS_vi": {
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"fields": [
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{"bits": [0, 0], "name": "SCC"},
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{"bits": [1, 2], "name": "SPI_PRIO"},
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{"bits": [3, 4], "name": "USER_PRIO"},
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{"bits": [5, 5], "name": "PRIV"},
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{"bits": [6, 6], "name": "TRAP_EN"},
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{"bits": [7, 7], "name": "TTRACE_EN"},
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{"bits": [8, 8], "name": "EXPORT_RDY"},
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{"bits": [9, 9], "name": "EXECZ"},
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{"bits": [10, 10], "name": "VCCZ"},
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{"bits": [11, 11], "name": "IN_TG"},
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{"bits": [12, 12], "name": "IN_BARRIER"},
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{"bits": [13, 13], "name": "HALT"},
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{"bits": [14, 14], "name": "TRAP"},
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{"bits": [15, 15], "name": "TTRACE_CU_EN"},
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{"bits": [16, 16], "name": "VALID"},
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{"bits": [17, 17], "name": "ECC_ERR"},
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{"bits": [18, 18], "name": "SKIP_EXPORT"},
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{"bits": [19, 19], "name": "PERF_EN"},
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{"bits": [20, 20], "name": "COND_DBG_USER"},
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{"bits": [21, 21], "name": "COND_DBG_SYS"},
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{"bits": [22, 22], "name": "ALLOW_REPLAY"},
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{"bits": [23, 23], "name": "INST_ATC"},
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{"bits": [27, 27], "name": "MUST_EXPORT"}
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]
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},
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"SQ_WAVE_IB_STS_cik_vi": {
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"fields": [
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{"bits": [0, 3], "name": "VM_CNT"},
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{"bits": [4, 6], "name": "EXP_CNT"},
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{"bits": [8, 11], "name": "LGKM_CNT"},
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{"bits": [12, 14], "name": "VALU_CNT"},
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{"bits": [15, 15], "name": "FIRST_REPLAY_vi"},
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{"bits": [16, 19], "name": "RCNT_vi"}
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]
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},
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"SQ_WAVE_HW_ID_cik_vi": {
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"fields": [
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{"bits": [0, 3], "name": "WAVE_ID"},
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{"bits": [4, 5], "name": "SIMD_ID"},
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{"bits": [6, 7], "name": "PIPE_ID"},
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{"bits": [8, 11], "name": "CU_ID"},
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{"bits": [12, 12], "name": "SH_ID"},
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{"bits": [13, 14], "name": "SE_ID"},
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{"bits": [16, 19], "name": "TG_ID"},
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{"bits": [20, 23], "name": "VM_ID"},
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{"bits": [24, 26], "name": "QUEUE_ID"},
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{"bits": [27, 29], "name": "STATE_ID"},
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{"bits": [30, 31], "name": "ME_ID"}
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]
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}
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}
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}
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