radv/gfx10: add gfx10_cs_emit_cache_flush
The cache flush logic on GFX10 is quite different and it's implemented with a new function. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
Bas Nieuwenhuizen
parent
b0b6e27bca
commit
7e43022e8c
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@ -823,6 +823,172 @@ si_emit_acquire_mem(struct radeon_cmdbuf *cs,
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}
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}
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static void
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gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
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enum chip_class chip_class,
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uint32_t *flush_cnt,
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uint64_t flush_va,
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bool is_mec,
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enum radv_cmd_flush_bits flush_bits,
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uint64_t gfx9_eop_bug_va)
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{
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uint32_t gcr_cntl = 0;
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unsigned cb_db_event = 0;
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/* We don't need these. */
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assert(!(flush_bits & (RADV_CMD_FLAG_VGT_FLUSH |
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RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
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if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
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gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
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if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
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/* TODO: When writing to the SMEM L1 cache, we need to set SEQ
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* to FORWARD when both L1 and L2 are written out (WB or INV).
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*/
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gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
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}
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if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
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gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
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if (flush_bits & RADV_CMD_FLAG_INV_L2) {
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/* Writeback and invalidate everything in L2. */
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gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
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} else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
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/* Writeback but do not invalidate. */
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gcr_cntl |= S_586_GL2_WB(1);
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}
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/* TODO: Implement this new flag for GFX9+.
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if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
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gcr_cntl |= S_586_GLM_INV(1);
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*/
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if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
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/* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
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if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
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/* Flush CMASK/FMASK/DCC. Will wait for idle later. */
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
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EVENT_INDEX(0));
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}
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/* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
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if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
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/* Flush HTILE. Will wait for idle later. */
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
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EVENT_INDEX(0));
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}
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/* First flush CB/DB, then L1/L2. */
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gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
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if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
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(RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
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cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
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} else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
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cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
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} else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
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cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
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} else {
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assert(0);
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}
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} else {
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/* Wait for graphics shaders to go idle if requested. */
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if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
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} else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
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}
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}
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if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
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}
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if (cb_db_event) {
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/* CB/DB flush and invalidate (or possibly just a wait for a
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* meta flush) via RELEASE_MEM.
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*
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* Combine this with other cache flushes when possible; this
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* requires affected shaders to be idle, so do it after the
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* CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
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* implied).
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*/
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/* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
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unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
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unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
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unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
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unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
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assert(G_586_GL2_US(gcr_cntl) == 0);
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assert(G_586_GL2_RANGE(gcr_cntl) == 0);
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assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
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unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
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unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
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unsigned gcr_seq = G_586_SEQ(gcr_cntl);
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gcr_cntl &= C_586_GLM_WB &
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C_586_GLM_INV &
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C_586_GLV_INV &
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C_586_GL1_INV &
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C_586_GL2_INV &
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C_586_GL2_WB; /* keep SEQ */
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assert(flush_cnt);
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(*flush_cnt)++;
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si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
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S_490_GLM_WB(glm_wb) |
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S_490_GLM_INV(glm_inv) |
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S_490_GLV_INV(glv_inv) |
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S_490_GL1_INV(gl1_inv) |
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S_490_GL2_INV(gl2_inv) |
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S_490_GL2_WB(gl2_wb) |
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S_490_SEQ(gcr_seq),
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EOP_DATA_SEL_VALUE_32BIT,
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flush_va, *flush_cnt,
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gfx9_eop_bug_va);
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radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
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*flush_cnt, 0xffffffff);
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}
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/* Ignore fields that only modify the behavior of other fields. */
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if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
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/* Flush caches and wait for the caches to assert idle.
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* The cache flush is executed in the ME, but the PFP waits
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* for completion.
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*/
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radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
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radeon_emit(cs, 0); /* CP_COHER_CNTL */
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radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
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radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
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radeon_emit(cs, 0); /* CP_COHER_BASE */
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radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
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radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
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radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
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} else if (cb_db_event ||
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(flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
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RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
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RADV_CMD_FLAG_CS_PARTIAL_FLUSH))) {
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/* We need to ensure that PFP waits as well. */
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radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
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radeon_emit(cs, 0);
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}
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if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
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EVENT_INDEX(0));
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} else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
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EVENT_INDEX(0));
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}
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}
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void
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si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
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enum chip_class chip_class,
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@ -835,7 +1001,14 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
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unsigned cp_coher_cntl = 0;
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uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
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RADV_CMD_FLAG_FLUSH_AND_INV_DB);
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if (chip_class >= GFX10) {
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/* GFX10 cache flush handling is quite different. */
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gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
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is_mec, flush_bits, gfx9_eop_bug_va);
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return;
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}
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if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
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cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
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if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
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