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radeon/llvm: Add DAG nodes for MIN instructions 

Also, remove the AMDIL MIN* instruction defs.
This commit is contained in:
Tom Stellard 2012-05-17 18:21:24 -04:00
parent 3f7a5ffac7
commit 7e3cd8df18
6 changed files with 38 additions and 14 deletions
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2
src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
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@ -55,7 +55,7 @@ my $FILE_TYPE = $ARGV[0];
open AMDIL, '<', 'AMDILInstructions.td';
my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32', 'BINARY_NOT_i32', 'MIN_f32');
my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32', 'BINARY_NOT_i32');
while (<AMDIL>) {
if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {

12
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
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@ -59,6 +59,15 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case AMDGPUIntrinsic::AMDGPU_umax:
return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
Op.getOperand(2));
case AMDGPUIntrinsic::AMDIL_min:
return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
Op.getOperand(2));
case AMDGPUIntrinsic::AMDGPU_imin:
return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
Op.getOperand(2));
case AMDGPUIntrinsic::AMDGPU_umin:
return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
Op.getOperand(2));
}
}
@ -108,5 +117,8 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const
NODE_NAME_CASE(FMAX)
NODE_NAME_CASE(SMAX)
NODE_NAME_CASE(UMAX)
NODE_NAME_CASE(FMIN)
NODE_NAME_CASE(SMIN)
NODE_NAME_CASE(UMIN)
}
}

3
src/gallium/drivers/radeon/AMDGPUISelLowering.h
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@ -55,6 +55,9 @@ enum
FMAX,
SMAX,
UMAX,
FMIN,
SMIN,
UMIN,
LAST_AMDGPU_ISD_NUMBER
};

15
src/gallium/drivers/radeon/AMDGPUInstrInfo.td
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@ -29,3 +29,18 @@ def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]
>;
// out = min(a, b) a and b are floats
def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,
[SDNPCommutative, SDNPAssociative]
>;
// out = min(a, b) a snd b are signed ints
def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]
>;
// out = min(a, b) a and b are unsigned ints
def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]
>;

6
src/gallium/drivers/radeon/AMDILInstructions.td
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@ -102,7 +102,6 @@ defm IMAD24 : TernaryIntrinsicInt<IL_OP_I_MAD24, int_AMDIL_mad24_i32>;
}
defm CARRY : BinaryIntrinsicInt<IL_OP_I_CARRY, int_AMDIL_carry_i32>;
defm BORROW : BinaryIntrinsicInt<IL_OP_I_BORROW, int_AMDIL_borrow_i32>;
defm IMIN : BinaryIntrinsicInt<IL_OP_I_MIN, int_AMDIL_min_i32>;
defm IMAX : BinaryIntrinsicInt<IL_OP_I_MAX, int_AMDIL_max_i32>;
defm IBIT_EXTRACT : TernaryIntrinsicInt<IL_OP_IBIT_EXTRACT,
int_AMDIL_bit_extract_i32>;
@ -137,7 +136,6 @@ defm UBIT_REVERSE : UnaryIntrinsicInt<IL_OP_UBIT_REVERSE,
defm UMULHI_INT : BinaryIntrinsicInt<IL_OP_U_MUL_HIGH, int_AMDIL_mulhi_u32>;
defm UMULHI24 : BinaryIntrinsicInt<IL_OP_U_MULHI24, int_AMDIL_mulhi24_u32>;
defm UMUL24 : BinaryIntrinsicInt<IL_OP_U_MUL24, int_AMDIL_mul24_u32>;
defm UMIN : BinaryIntrinsicInt<IL_OP_U_MIN, int_AMDIL_min_u32>;
defm UMAX : BinaryIntrinsicInt<IL_OP_U_MAX, int_AMDIL_max_u32>;
defm UBIT_EXTRACT : TernaryIntrinsicInt<IL_OP_UBIT_EXTRACT,
int_AMDIL_bit_extract_u32>;
@ -169,8 +167,6 @@ def LADD : TwoInOneOut<IL_OP_I64_ADD, (outs GPRI64:$dst),
(ins GPRI64:$src1, GPRI64:$src2),
!strconcat(IL_OP_I64_ADD.Text, " $dst, $src1, $src2"),
[(set GPRI64:$dst, (IL_add GPRI64:$src1, GPRI64:$src2))]>;
defm IMIN64 : BinaryIntrinsicLong<IL_OP_I64_MIN, int_AMDIL_min_i32>;
defm UMIN64 : BinaryIntrinsicLong<IL_OP_U64_MIN, int_AMDIL_min_u32>;
defm IMAX64 : BinaryIntrinsicLong<IL_OP_I64_MAX, int_AMDIL_max_i32>;
defm UMAX64 : BinaryIntrinsicLong<IL_OP_U64_MAX, int_AMDIL_max_u32>;
}
@ -250,7 +246,6 @@ defm POW : BinaryIntrinsicFloat<IL_OP_POW, int_AMDIL_pow>;
let hasIEEEFlag = 1 in {
let mayLoad = 0, mayStore=0 in {
defm MIN : BinaryIntrinsicFloat<IL_OP_MIN, int_AMDIL_min>;
}
defm MOD : BinaryOpMCf32<IL_OP_MOD, frem>;
}
@ -367,7 +362,6 @@ def NEG_v2f64 : OneInOneOut<IL_OP_MOV, (outs GPRV2F64:$dst),
!strconcat(IL_OP_MOV.Text, " $dst, $src0"),
[(set GPRV2F64:$dst, (fneg GPRV2F64:$src0))]>;
let mayLoad = 0, mayStore=0 in {
defm MIN : BinaryIntrinsicDouble<IL_OP_D_MIN, int_AMDIL_min>;
defm MAX : BinaryIntrinsicDouble<IL_OP_D_MAX, int_AMDIL_max>;
defm DIV : BinaryIntrinsicDouble<IL_OP_D_DIV, int_AMDIL_div>;
defm MAD : TernaryIntrinsicDouble<IL_OP_D_MAD, int_AMDIL_mad>;

14
src/gallium/drivers/radeon/R600Instructions.td
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@ -265,9 +265,8 @@ def MAX : R600_2OP <
def MIN : R600_2OP <
0x4, "MIN",
[(set R600_Reg32:$dst, (int_AMDIL_min R600_Reg32:$src0, R600_Reg32:$src1))]> {
let AMDILOp = AMDILInst.MIN_f32;
}
[(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
>;
/* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
* so some of the instruction names don't match the asm string.
@ -372,16 +371,17 @@ def MAX_INT : R600_2OP <
def MIN_INT : R600_2OP <
0x37, "MIN_INT",
[(set R600_Reg32:$dst, (int_AMDGPU_imin R600_Reg32:$src0, R600_Reg32:$src1))]>;
[(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>;
def MAX_UINT : R600_2OP <
0x38, "MAX_UINT",
[(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
[(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]
>;
def MIN_UINT : R600_2OP <
0x39, "MIN_UINT",
[(set R600_Reg32:$dst, (int_AMDGPU_umin R600_Reg32:$src0, R600_Reg32:$src1))]>;
[(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))]
>;
def SETE_INT : R600_2OP <
0x3A, "SETE_INT",