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i965/gen6: Use isl for hiz 

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Topi Pohjolainen 2017-01-02 15:41:36 +02:00
parent 59e5519afa
commit 7e25410563
4 changed files with 27 additions and 40 deletions
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9
src/mesa/drivers/dri/i965/brw_blorp.c
View File

@ -165,8 +165,13 @@ blorp_surf_for_miptree(struct brw_context *brw,
surf->aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
struct isl_surf *aux_surf = &tmp_surfs[1];
intel_miptree_get_aux_isl_surf(brw, mt, surf->aux_usage, aux_surf);
struct isl_surf *aux_surf;
if (brw->gen == 6 && mt->hiz_buf) {
aux_surf = &mt->hiz_buf->aux_base.surf;
} else {
aux_surf = &tmp_surfs[1];
intel_miptree_get_aux_isl_surf(brw, mt, surf->aux_usage, aux_surf);
}
if (wants_resolve) {
bool supports_aux = surf->aux_usage != ISL_AUX_USAGE_NONE &&

12
src/mesa/drivers/dri/i965/gen6_depth_state.c
View File

@ -165,18 +165,14 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
/* Emit hiz buffer. */
if (hiz) {
assert(depth_mt);
struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt;
assert(hiz_mt->array_layout == GEN6_HIZ_STENCIL);
const uint32_t offset = intel_miptree_get_aligned_offset(
hiz_mt,
hiz_mt->level[lod].level_x,
hiz_mt->level[lod].level_y);
uint32_t offset;
isl_surf_get_image_offset_B_tile_sa(&depth_mt->hiz_buf->aux_base.surf,
lod, 0, 0, &offset, NULL, NULL);
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(depth_mt->hiz_buf->aux_base.pitch - 1);
OUT_BATCH(depth_mt->hiz_buf->aux_base.surf.row_pitch - 1);
OUT_RELOC(depth_mt->hiz_buf->aux_base.bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
offset);

39
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View File

@ -1078,10 +1078,7 @@ intel_miptree_hiz_buffer_free(struct intel_miptree_hiz_buffer *hiz_buf)
if (hiz_buf == NULL)
return;
if (hiz_buf->mt)
intel_miptree_release(&hiz_buf->mt);
else
brw_bo_unreference(hiz_buf->aux_base.bo);
brw_bo_unreference(hiz_buf->aux_base.bo);
free(hiz_buf);
}
@ -2025,34 +2022,26 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
struct intel_miptree_hiz_buffer *buf = calloc(sizeof(*buf), 1);
uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
if (brw->gen == 6)
layout_flags |= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL;
if (!buf)
return NULL;
layout_flags |= MIPTREE_LAYOUT_TILING_ANY;
buf->mt = intel_miptree_create(brw,
mt->target,
mt->format,
mt->first_level,
mt->last_level,
mt->logical_width0,
mt->logical_height0,
mt->logical_depth0,
mt->num_samples,
layout_flags);
if (!buf->mt) {
struct isl_surf temp_main_surf;
intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);
if (!isl_surf_get_hiz_surf(&brw->isl_dev, &temp_main_surf,
&buf->aux_base.surf)) {
free(buf);
return NULL;
}
buf->aux_base.bo = buf->mt->bo;
buf->aux_base.size = buf->mt->total_height * buf->mt->pitch;
buf->aux_base.pitch = buf->mt->pitch;
buf->aux_base.qpitch = buf->mt->qpitch * 2;
struct isl_surf *surf = &buf->aux_base.surf;
buf->aux_base.bo = brw_bo_alloc_tiled(brw->bufmgr, "hiz", surf->size,
I915_TILING_Y, surf->row_pitch,
BO_ALLOC_FOR_RENDER);
if (!buf->aux_base.bo) {
free(buf);
return NULL;
}
return buf;
}

7
src/mesa/drivers/dri/i965/intel_mipmap_tree.h
View File

@ -307,6 +307,8 @@ enum intel_aux_disable {
*/
struct intel_miptree_aux_buffer
{
struct isl_surf surf;
/**
* Buffer object containing the pixel data.
*
@ -360,11 +362,6 @@ struct intel_miptree_aux_buffer
struct intel_miptree_hiz_buffer
{
struct intel_miptree_aux_buffer aux_base;
/**
* Hiz miptree. Used only by Gen6.
*/
struct intel_mipmap_tree *mt;
};
struct intel_mipmap_tree