radv: switch to using radv_create_shaders()
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
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d1c9f30d7f
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7d45d22fdd
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@ -1361,7 +1361,7 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
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}
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}
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static struct ac_shader_variant_key
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static struct ac_shader_variant_key
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radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
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radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls)
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{
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{
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struct ac_shader_variant_key key;
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struct ac_shader_variant_key key;
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const VkPipelineVertexInputStateCreateInfo *input_state =
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const VkPipelineVertexInputStateCreateInfo *input_state =
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@ -1371,7 +1371,6 @@ radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es,
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key.vs.instance_rate_inputs = 0;
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key.vs.instance_rate_inputs = 0;
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key.vs.as_es = as_es;
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key.vs.as_es = as_es;
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key.vs.as_ls = as_ls;
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key.vs.as_ls = as_ls;
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key.vs.export_prim_id = export_prim_id;
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for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
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for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
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unsigned binding;
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unsigned binding;
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@ -1881,7 +1880,6 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
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const struct radv_graphics_pipeline_create_info *extra,
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const struct radv_graphics_pipeline_create_info *extra,
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const VkAllocationCallbacks *alloc)
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const VkAllocationCallbacks *alloc)
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{
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{
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struct radv_shader_module fs_m = {0};
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VkResult result;
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VkResult result;
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bool has_view_index = false;
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bool has_view_index = false;
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@ -1899,100 +1897,50 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
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radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
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radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
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const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
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const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
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struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
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for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
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for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
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gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
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gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
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pStages[stage] = &pCreateInfo->pStages[i];
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pStages[stage] = &pCreateInfo->pStages[i];
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modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
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}
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}
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if (!modules[MESA_SHADER_FRAGMENT]) {
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struct ac_shader_variant_key keys[MESA_SHADER_STAGES];
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nir_builder fs_b;
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memset(keys, 0, sizeof(keys));
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nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
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fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
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fs_m.nir = fs_b.shader;
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modules[MESA_SHADER_FRAGMENT] = &fs_m;
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}
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if (modules[MESA_SHADER_FRAGMENT]) {
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if (pStages[MESA_SHADER_VERTEX]) {
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struct ac_shader_variant_key key = {0};
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key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
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if (pCreateInfo->pMultisampleState &&
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pCreateInfo->pMultisampleState->rasterizationSamples > 1)
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key.fs.multisample = true;
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if (pipeline->device->physical_device->rad_info.chip_class < VI)
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radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);
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const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
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pipeline->shaders[MESA_SHADER_FRAGMENT] =
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radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
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stage ? stage->pName : "main",
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MESA_SHADER_FRAGMENT,
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stage ? stage->pSpecializationInfo : NULL,
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pipeline->layout, &key);
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pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
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}
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if (fs_m.nir)
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ralloc_free(fs_m.nir);
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if (modules[MESA_SHADER_VERTEX]) {
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bool as_es = false;
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bool as_es = false;
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bool as_ls = false;
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bool as_ls = false;
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bool export_prim_id = false;
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if (pStages[MESA_SHADER_TESS_CTRL])
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if (modules[MESA_SHADER_TESS_CTRL])
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as_ls = true;
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as_ls = true;
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else if (modules[MESA_SHADER_GEOMETRY])
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else if (pStages[MESA_SHADER_GEOMETRY])
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as_es = true;
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as_es = true;
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else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
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export_prim_id = true;
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struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
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key.has_multiview_view_index = has_view_index;
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pipeline->shaders[MESA_SHADER_VERTEX] =
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keys[MESA_SHADER_VERTEX] = radv_compute_vs_key(pCreateInfo, as_es, as_ls);
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radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
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keys[MESA_SHADER_VERTEX].has_multiview_view_index = has_view_index;
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pStages[MESA_SHADER_VERTEX]->pName,
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MESA_SHADER_VERTEX,
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pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
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pipeline->layout, &key);
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pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
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}
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}
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if (modules[MESA_SHADER_GEOMETRY]) {
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if (pStages[MESA_SHADER_TESS_EVAL]) {
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struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
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keys[MESA_SHADER_TESS_EVAL].has_multiview_view_index = has_view_index;
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key.has_multiview_view_index = has_view_index;
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if (pStages[MESA_SHADER_GEOMETRY])
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keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
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pipeline->shaders[MESA_SHADER_GEOMETRY] =
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radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
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pStages[MESA_SHADER_GEOMETRY]->pName,
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MESA_SHADER_GEOMETRY,
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pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
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pipeline->layout, &key);
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pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
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}
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}
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if (modules[MESA_SHADER_TESS_EVAL]) {
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if (pCreateInfo->pTessellationState)
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assert(modules[MESA_SHADER_TESS_CTRL]);
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keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
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radv_tess_pipeline_compile(pipeline,
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if (pStages[MESA_SHADER_GEOMETRY]) {
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cache,
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keys[MESA_SHADER_GEOMETRY] = radv_compute_vs_key(pCreateInfo, false, false);
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modules[MESA_SHADER_TESS_CTRL],
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keys[MESA_SHADER_GEOMETRY].has_multiview_view_index = has_view_index;
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modules[MESA_SHADER_TESS_EVAL],
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pStages[MESA_SHADER_TESS_CTRL]->pName,
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pStages[MESA_SHADER_TESS_EVAL]->pName,
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pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
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pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
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pipeline->layout,
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pCreateInfo->pTessellationState->patchControlPoints,
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has_view_index);
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pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
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mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
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}
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}
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if (pCreateInfo->pMultisampleState &&
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pCreateInfo->pMultisampleState->rasterizationSamples > 1)
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keys[MESA_SHADER_FRAGMENT].fs.multisample = true;
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keys[MESA_SHADER_FRAGMENT].fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
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if (pipeline->device->physical_device->rad_info.chip_class < VI)
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radv_pipeline_compute_get_int_clamp(pCreateInfo, &keys[MESA_SHADER_FRAGMENT].fs.is_int8, &keys[MESA_SHADER_FRAGMENT].fs.is_int10);
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radv_create_shaders(pipeline, device, cache, keys, pStages);
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radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
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radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
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radv_pipeline_init_raster_state(pipeline, pCreateInfo);
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radv_pipeline_init_raster_state(pipeline, pCreateInfo);
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radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
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radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
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@ -2310,7 +2258,7 @@ static VkResult radv_compute_pipeline_create(
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{
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{
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RADV_FROM_HANDLE(radv_device, device, _device);
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RADV_FROM_HANDLE(radv_device, device, _device);
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RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
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RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
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RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
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const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
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struct radv_pipeline *pipeline;
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struct radv_pipeline *pipeline;
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VkResult result;
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VkResult result;
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@ -2323,12 +2271,8 @@ static VkResult radv_compute_pipeline_create(
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pipeline->device = device;
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pipeline->device = device;
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pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
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pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
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pipeline->shaders[MESA_SHADER_COMPUTE] =
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pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
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radv_pipeline_compile(pipeline, cache, module,
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radv_create_shaders(pipeline, device, cache, NULL, pStages);
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pCreateInfo->stage.pName,
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MESA_SHADER_COMPUTE,
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pCreateInfo->stage.pSpecializationInfo,
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pipeline->layout, NULL);
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pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
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pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
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