i965: Combine URB code emission into a single group.
All four URB packets need to be programmed together in order for the GPU state to be valid. Putting them in separate BEGIN..ADVANCE blocks is risky: if we're nearing the end of a batch, the batch could be flushed inbetween two of the commands, causing the URB programming to be split into two batchbuffers. This -might- be okay with hardware contexts, but it offers no advantages over keeping them together, and has a potential for hangs. Putting them into a single BEGIN..ADVANCE block ensures they'll be kept in the same batch, which seems wise. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
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@ -60,12 +60,10 @@ gen7_allocate_push_constants(struct brw_context *brw)
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if (brw->is_haswell && brw->gt == 3)
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size = 16;
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BEGIN_BATCH(2);
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BEGIN_BATCH(4);
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OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2));
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OUT_BATCH(size);
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ADVANCE_BATCH();
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BEGIN_BATCH(2);
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OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2));
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OUT_BATCH(size | size << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
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ADVANCE_BATCH();
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@ -105,27 +103,21 @@ void
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gen7_emit_urb_state(struct brw_context *brw, GLuint nr_vs_entries,
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GLuint vs_size, GLuint vs_start)
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{
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BEGIN_BATCH(2);
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BEGIN_BATCH(8);
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OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2));
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OUT_BATCH(nr_vs_entries |
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((vs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
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(vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
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ADVANCE_BATCH();
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/* Allocate the GS, HS, and DS zero space - we don't use them. */
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BEGIN_BATCH(2);
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OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2));
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OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
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(vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
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ADVANCE_BATCH();
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BEGIN_BATCH(2);
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OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2));
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OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
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(vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
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ADVANCE_BATCH();
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BEGIN_BATCH(2);
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OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2));
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OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
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(vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
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