pvr: Add initial implementation of vkCmdDispatch().
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com> Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com> Reviewed-by: Frank Binns <frank.binns@imgtec.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16040>
This commit is contained in:
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commit
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@ -2496,75 +2496,13 @@ VkResult pvr_cmd_buffer_add_transfer_cmd(struct pvr_cmd_buffer *cmd_buffer,
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return VK_SUCCESS;
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}
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void pvr_CmdDispatch(VkCommandBuffer commandBuffer,
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uint32_t groupCountX,
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uint32_t groupCountY,
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uint32_t groupCountZ)
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{
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assert(!"Unimplemented");
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}
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void pvr_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
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VkBuffer _buffer,
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VkDeviceSize offset)
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{
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assert(!"Unimplemented");
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}
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void pvr_CmdDraw(VkCommandBuffer commandBuffer,
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uint32_t vertexCount,
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uint32_t instanceCount,
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uint32_t firstVertex,
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uint32_t firstInstance)
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{
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assert(!"Unimplemented");
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}
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static void
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pvr_update_draw_state(struct pvr_cmd_buffer_state *const state,
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const struct pvr_cmd_buffer_draw_state *const draw_state)
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pvr_validate_push_descriptors(struct pvr_cmd_buffer *cmd_buffer,
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bool *const push_descriptors_dirty_out)
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{
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/* We don't have a state to tell us that base_instance is being used so it
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* gets used as a boolean - 0 means we'll use a pds program that skips the
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* base instance addition. If the base_instance gets used (and the last
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* draw's base_instance was 0) then we switch to the BASE_INSTANCE attrib
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* program.
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*
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* If base_instance changes then we only need to update the data section.
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*
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* The only draw call state that doesn't really matter is the start vertex
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* as that is handled properly in the VDM state in all cases.
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*/
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if ((state->draw_state.draw_indexed != draw_state->draw_indexed) ||
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(state->draw_state.draw_indirect != draw_state->draw_indirect) ||
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(state->draw_state.base_instance == 0 &&
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draw_state->base_instance != 0)) {
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state->dirty.draw_variant = true;
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} else if (state->draw_state.base_instance != draw_state->base_instance) {
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state->dirty.draw_base_instance = true;
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}
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state->draw_state = *draw_state;
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}
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static uint32_t pvr_calc_shared_regs_count(
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const struct pvr_graphics_pipeline *const gfx_pipeline)
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{
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const struct pvr_pipeline_stage_state *const vertex_state =
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&gfx_pipeline->vertex_shader_state.stage_state;
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uint32_t shared_regs = vertex_state->const_shared_reg_count +
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vertex_state->const_shared_reg_offset;
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if (gfx_pipeline->fragment_shader_state.bo) {
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const struct pvr_pipeline_stage_state *const fragment_state =
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&gfx_pipeline->fragment_shader_state.stage_state;
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uint32_t fragment_regs = fragment_state->const_shared_reg_count +
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fragment_state->const_shared_reg_offset;
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shared_regs = MAX2(shared_regs, fragment_regs);
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}
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return shared_regs;
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/* TODO: Implement this function, based on ValidatePushDescriptors. */
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pvr_finishme("Add support for push descriptors!");
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*push_descriptors_dirty_out = false;
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}
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#define PVR_WRITE(_buffer, _value, _offset, _max) \
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@ -2694,10 +2632,10 @@ static VkResult pvr_setup_descriptor_mappings(
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struct pvr_cmd_buffer *const cmd_buffer,
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enum pvr_stage_allocation stage,
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const struct pvr_stage_allocation_uniform_state *uniform_state,
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UNUSED const pvr_dev_addr_t *const num_worgroups_buff_addr,
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uint32_t *const uniform_data_offset_out)
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{
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const struct pvr_pds_info *const pds_info = &uniform_state->pds_info;
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const struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
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const struct pvr_descriptor_state *desc_state;
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const uint8_t *entries;
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uint32_t *dword_buffer;
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@ -2705,6 +2643,8 @@ static VkResult pvr_setup_descriptor_mappings(
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struct pvr_bo *pvr_bo;
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VkResult result;
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pvr_finishme("Handle num_worgroups_buff_addr");
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if (!pds_info->data_size_in_dwords)
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return VK_SUCCESS;
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@ -2740,6 +2680,13 @@ static VkResult pvr_setup_descriptor_mappings(
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const struct pvr_const_map_entry *const entry_header =
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(struct pvr_const_map_entry *)entries;
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/* TODO: See if instead of reusing the blend constant buffer type entry,
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* we can setup a new buffer type specifically for num_workgroups or other
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* built-in variables. The mappings are setup at pipeline creation when
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* creating the uniform program.
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*/
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pvr_finishme("Handle blend constant reuse for compute.");
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switch (entry_header->type) {
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case PVR_PDS_CONST_MAP_ENTRY_TYPE_LITERAL32: {
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const struct pvr_const_map_entry_literal32 *const literal =
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@ -2766,7 +2713,7 @@ static VkResult pvr_setup_descriptor_mappings(
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/* TODO: Handle push descriptors. */
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assert(desc_set < PVR_MAX_DESCRIPTOR_SETS);
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descriptor_set = state->gfx_desc_state.descriptor_sets[desc_set];
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descriptor_set = desc_state->descriptor_sets[desc_set];
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/* TODO: Handle dynamic buffers. */
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descriptor = &descriptor_set->descriptors[binding];
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@ -2878,6 +2825,144 @@ static VkResult pvr_setup_descriptor_mappings(
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#undef PVR_WRITE
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void pvr_CmdDispatch(VkCommandBuffer commandBuffer,
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uint32_t groupCountX,
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uint32_t groupCountY,
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uint32_t groupCountZ)
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{
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const uint32_t workgroup_size[] = { groupCountX, groupCountY, groupCountZ };
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PVR_FROM_HANDLE(pvr_cmd_buffer, cmd_buffer, commandBuffer);
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struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
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const struct pvr_compute_pipeline *compute_pipeline =
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state->compute_pipeline;
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const VkShaderStageFlags push_consts_stage_mask =
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compute_pipeline->base.layout->push_constants_shader_stages;
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bool push_descriptors_dirty;
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struct pvr_sub_cmd *sub_cmd;
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VkResult result;
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PVR_CHECK_COMMAND_BUFFER_BUILDING_STATE(cmd_buffer);
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assert(compute_pipeline);
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if (!groupCountX || !groupCountY || !groupCountZ)
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return;
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pvr_cmd_buffer_start_sub_cmd(cmd_buffer, PVR_SUB_CMD_TYPE_COMPUTE);
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sub_cmd = state->current_sub_cmd;
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sub_cmd->compute.uses_atomic_ops |=
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compute_pipeline->state.shader.uses_atomic_ops;
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sub_cmd->compute.uses_barrier |= compute_pipeline->state.shader.uses_barrier;
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if (push_consts_stage_mask & VK_SHADER_STAGE_COMPUTE_BIT) {
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/* TODO: Add a dirty push constants mask in the cmd_buffer state and
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* check for dirty compute stage.
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*/
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pvr_finishme("Add support for push constants.");
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}
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pvr_validate_push_descriptors(cmd_buffer, &push_descriptors_dirty);
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if (compute_pipeline->state.shader.uses_num_workgroups) {
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struct pvr_bo *num_workgroups_bo;
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result = pvr_cmd_buffer_upload_general(cmd_buffer,
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workgroup_size,
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sizeof(workgroup_size),
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&num_workgroups_bo);
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if (result != VK_SUCCESS)
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return;
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result =
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pvr_setup_descriptor_mappings(cmd_buffer,
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PVR_STAGE_ALLOCATION_COMPUTE,
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&compute_pipeline->state.uniform,
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&num_workgroups_bo->vma->dev_addr,
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&state->pds_compute_uniform_data_offset);
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if (result != VK_SUCCESS)
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return;
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} else if ((compute_pipeline->base.layout
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->per_stage_descriptor_masks[PVR_STAGE_ALLOCATION_COMPUTE] &&
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state->dirty.compute_desc_dirty) ||
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state->dirty.compute_pipeline_binding || push_descriptors_dirty) {
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result =
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pvr_setup_descriptor_mappings(cmd_buffer,
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PVR_STAGE_ALLOCATION_COMPUTE,
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&compute_pipeline->state.uniform,
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NULL,
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&state->pds_compute_uniform_data_offset);
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if (result != VK_SUCCESS)
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return;
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}
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/* FIXME: Create shared update kernel end emit control stream. */
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/* FIXME: Create update kernel end emit control stream. */
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}
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void pvr_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
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VkBuffer _buffer,
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VkDeviceSize offset)
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{
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assert(!"Unimplemented");
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}
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void pvr_CmdDraw(VkCommandBuffer commandBuffer,
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uint32_t vertexCount,
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uint32_t instanceCount,
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uint32_t firstVertex,
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uint32_t firstInstance)
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{
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assert(!"Unimplemented");
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}
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static void
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pvr_update_draw_state(struct pvr_cmd_buffer_state *const state,
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const struct pvr_cmd_buffer_draw_state *const draw_state)
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{
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/* We don't have a state to tell us that base_instance is being used so it
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* gets used as a boolean - 0 means we'll use a pds program that skips the
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* base instance addition. If the base_instance gets used (and the last
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* draw's base_instance was 0) then we switch to the BASE_INSTANCE attrib
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* program.
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*
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* If base_instance changes then we only need to update the data section.
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*
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* The only draw call state that doesn't really matter is the start vertex
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* as that is handled properly in the VDM state in all cases.
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*/
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if ((state->draw_state.draw_indexed != draw_state->draw_indexed) ||
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(state->draw_state.draw_indirect != draw_state->draw_indirect) ||
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(state->draw_state.base_instance == 0 &&
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draw_state->base_instance != 0)) {
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state->dirty.draw_variant = true;
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} else if (state->draw_state.base_instance != draw_state->base_instance) {
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state->dirty.draw_base_instance = true;
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}
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state->draw_state = *draw_state;
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}
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static uint32_t pvr_calc_shared_regs_count(
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const struct pvr_graphics_pipeline *const gfx_pipeline)
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{
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const struct pvr_pipeline_stage_state *const vertex_state =
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&gfx_pipeline->vertex_shader_state.stage_state;
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uint32_t shared_regs = vertex_state->const_shared_reg_count +
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vertex_state->const_shared_reg_offset;
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if (gfx_pipeline->fragment_shader_state.bo) {
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const struct pvr_pipeline_stage_state *const fragment_state =
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&gfx_pipeline->fragment_shader_state.stage_state;
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uint32_t fragment_regs = fragment_state->const_shared_reg_count +
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fragment_state->const_shared_reg_offset;
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shared_regs = MAX2(shared_regs, fragment_regs);
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}
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return shared_regs;
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}
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static void
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pvr_emit_dirty_pds_state(const struct pvr_cmd_buffer *const cmd_buffer,
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const uint32_t pds_vertex_uniform_data_offset)
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@ -3962,15 +4047,6 @@ pvr_emit_dirty_ppp_state(struct pvr_cmd_buffer *const cmd_buffer)
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return VK_SUCCESS;
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}
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static void
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pvr_validate_push_descriptors(struct pvr_cmd_buffer *cmd_buffer,
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bool *const push_descriptors_dirty_out)
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{
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/* TODO: Implement this function, based on ValidatePushDescriptors. */
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pvr_finishme("Add support for push descriptors!");
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*push_descriptors_dirty_out = false;
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}
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static void
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pvr_calculate_vertex_cam_size(const struct pvr_device_info *dev_info,
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const uint32_t vs_output_size,
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@ -4284,6 +4360,7 @@ static VkResult pvr_validate_draw_state(struct pvr_cmd_buffer *cmd_buffer)
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cmd_buffer,
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PVR_STAGE_ALLOCATION_FRAGMENT,
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&state->gfx_pipeline->fragment_shader_state.uniform_state,
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NULL,
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&state->pds_fragment_uniform_data_offset);
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if (result != VK_SUCCESS) {
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mesa_loge("Could not setup fragment descriptor mappings.");
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@ -4298,6 +4375,7 @@ static VkResult pvr_validate_draw_state(struct pvr_cmd_buffer *cmd_buffer)
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cmd_buffer,
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PVR_STAGE_ALLOCATION_VERTEX_GEOMETRY,
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&state->gfx_pipeline->vertex_shader_state.uniform_state,
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NULL,
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&pds_vertex_uniform_data_offset);
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if (result != VK_SUCCESS) {
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mesa_loge("Could not setup vertex descriptor mappings.");
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@ -957,11 +957,16 @@ static VkResult pvr_compute_pipeline_compile(
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/* FIXME: Compile the shader. */
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/* FIXME: Remove this hard coding. */
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compute_pipeline->state.shader.uses_atomic_ops = false;
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compute_pipeline->state.shader.uses_barrier = false;
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compute_pipeline->state.shader.uses_num_workgroups = false;
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result = pvr_gpu_upload_usc(device,
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pvr_usc_compute_shader,
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sizeof(pvr_usc_compute_shader),
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cache_line_size,
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&compute_pipeline->state.bo);
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&compute_pipeline->state.shader.bo);
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if (result != VK_SUCCESS)
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return result;
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@ -1007,7 +1012,7 @@ static VkResult pvr_compute_pipeline_compile(
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barrier_coefficient,
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false,
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pvr_pds_compute_program_params.usc_temps,
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compute_pipeline->state.bo->vma->dev_addr,
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compute_pipeline->state.shader.bo->vma->dev_addr,
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&compute_pipeline->state.primary_program,
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&compute_pipeline->state.primary_program_info,
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NULL);
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@ -1031,7 +1036,7 @@ static VkResult pvr_compute_pipeline_compile(
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barrier_coefficient,
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true,
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pvr_pds_compute_program_params.usc_temps,
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compute_pipeline->state.bo->vma->dev_addr,
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compute_pipeline->state.shader.bo->vma->dev_addr,
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&compute_pipeline->state.primary_program_base_workgroup_variant,
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&compute_pipeline->state.primary_program_base_workgroup_variant_info,
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&compute_pipeline->state.base_workgroup_ids_dword_offset);
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@ -1049,7 +1054,7 @@ err_free_uniform_program:
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pvr_bo_free(device, compute_pipeline->state.uniform.pds_code.pvr_bo);
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err_free_shader:
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pvr_bo_free(device, compute_pipeline->state.bo);
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pvr_bo_free(device, compute_pipeline->state.shader.bo);
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return result;
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}
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@ -1139,7 +1144,7 @@ static void pvr_compute_pipeline_destroy(
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allocator,
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&compute_pipeline->state.uniform.pds_code,
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&compute_pipeline->state.uniform.pds_info);
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pvr_bo_free(device, compute_pipeline->state.bo);
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pvr_bo_free(device, compute_pipeline->state.shader.bo);
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pvr_pipeline_finish(&compute_pipeline->base);
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@ -137,11 +137,11 @@ enum pvr_pipeline_stage_bits {
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#define PVR_PIPELINE_STAGE_ALL_GRAPHICS_BITS \
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(PVR_PIPELINE_STAGE_GEOM_BIT | PVR_PIPELINE_STAGE_FRAG_BIT)
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#define PVR_PIPELINE_STAGE_ALL_BITS \
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(PVR_PIPELINE_STAGE_ALL_GRAPHICS_BITS | PVR_PIPELINE_STAGE_TRANSFER_BIT)
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#define PVR_PIPELINE_STAGE_ALL_BITS \
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(PVR_PIPELINE_STAGE_ALL_GRAPHICS_BITS | PVR_PIPELINE_STAGE_COMPUTE_BIT | \
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PVR_PIPELINE_STAGE_TRANSFER_BIT)
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/* TODO: This number must be changed when we add compute support. */
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#define PVR_NUM_SYNC_PIPELINE_STAGES 3U
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#define PVR_NUM_SYNC_PIPELINE_STAGES 4U
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/* Warning: Do not define an invalid stage as 0 since other code relies on 0
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* being the first shader stage. This allows for stages to be split or added
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@ -858,6 +858,7 @@ struct pvr_cmd_buffer_state {
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uint32_t pds_vertex_attrib_offset;
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uint32_t pds_fragment_uniform_data_offset;
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uint32_t pds_compute_uniform_data_offset;
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};
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static_assert(
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@ -1025,8 +1026,15 @@ struct pvr_compute_pipeline {
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struct pvr_pipeline base;
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struct {
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/* Pointer to a buffer object that contains the shader binary. */
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struct pvr_bo *bo;
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struct {
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/* Pointer to a buffer object that contains the shader binary. */
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struct pvr_bo *bo;
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bool uses_atomic_ops;
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bool uses_barrier;
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/* E.g. GLSL shader uses gl_NumWorkGroups. */
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bool uses_num_workgroups;
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} shader;
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struct {
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uint32_t base_workgroup : 1;
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@ -329,7 +329,7 @@ pvr_convert_stage_mask(VkPipelineStageFlags stage_mask)
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if (stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
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VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT)) {
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assert(!"Unimplemented");
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stages |= PVR_PIPELINE_STAGE_COMPUTE_BIT;
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}
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if (stage_mask & (VK_PIPELINE_STAGE_TRANSFER_BIT))
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@ -667,6 +667,8 @@ static VkResult pvr_process_empty_job(
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uint32_t *stage_flags,
|
||||
struct pvr_winsys_syncobj *completions[static PVR_JOB_TYPE_MAX])
|
||||
{
|
||||
STATIC_ASSERT(PVR_JOB_TYPE_MAX >= PVR_NUM_SYNC_PIPELINE_STAGES);
|
||||
|
||||
for (uint32_t i = 0; i < semaphore_count; i++) {
|
||||
PVR_FROM_HANDLE(pvr_semaphore, semaphore, semaphores[i]);
|
||||
|
||||
|
|
Loading…
Reference in New Issue