radv: Determine unneeded dynamic states.
Which avoids setting or emitting them. Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
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0a89784bcc
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7c366bc152
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@ -1218,20 +1218,18 @@ radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
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static void
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static void
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radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
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radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
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{
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{
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struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
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struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
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struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
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unsigned slope = fui(d->depth_bias.slope * 16.0f);
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unsigned slope = fui(d->depth_bias.slope * 16.0f);
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unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
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unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
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if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
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radeon_set_context_reg_seq(cmd_buffer->cs,
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radeon_set_context_reg_seq(cmd_buffer->cs,
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R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
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R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
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radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
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radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
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radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
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radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
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radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
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radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
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radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
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radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
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radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
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radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
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}
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}
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}
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static void
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static void
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@ -1633,37 +1631,35 @@ void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
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static void
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static void
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radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
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radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
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{
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{
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if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
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uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
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return;
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if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
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if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
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radv_emit_viewport(cmd_buffer);
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radv_emit_viewport(cmd_buffer);
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if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
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if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
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radv_emit_scissor(cmd_buffer);
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radv_emit_scissor(cmd_buffer);
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if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
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if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
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radv_emit_line_width(cmd_buffer);
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radv_emit_line_width(cmd_buffer);
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if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
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if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
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radv_emit_blend_constants(cmd_buffer);
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radv_emit_blend_constants(cmd_buffer);
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if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
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if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
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RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
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RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
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RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
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RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
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radv_emit_stencil(cmd_buffer);
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radv_emit_stencil(cmd_buffer);
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if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
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if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
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radv_emit_depth_bounds(cmd_buffer);
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radv_emit_depth_bounds(cmd_buffer);
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if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
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if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
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RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
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radv_emit_depth_bias(cmd_buffer);
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radv_emit_depth_bias(cmd_buffer);
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if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
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if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
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radv_emit_discard_rectangle(cmd_buffer);
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radv_emit_discard_rectangle(cmd_buffer);
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cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
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cmd_buffer->state.dirty &= ~states;
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}
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}
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static void
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static void
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@ -1031,15 +1031,48 @@ static unsigned radv_dynamic_state_mask(VkDynamicState state)
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}
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}
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}
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}
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static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
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{
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uint32_t states = RADV_DYNAMIC_ALL;
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/* If rasterization is disabled we do not care about any of the dynamic states,
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* since they are all rasterization related only. */
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if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
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return 0;
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if (!pCreateInfo->pRasterizationState->depthBiasEnable)
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states &= ~RADV_DYNAMIC_DEPTH_BIAS;
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if (!pCreateInfo->pDepthStencilState ||
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!pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
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states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
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if (!pCreateInfo->pDepthStencilState ||
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!pCreateInfo->pDepthStencilState->stencilTestEnable)
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states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
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RADV_DYNAMIC_STENCIL_WRITE_MASK |
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RADV_DYNAMIC_STENCIL_REFERENCE);
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if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
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states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
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/* TODO: blend constants & line width. */
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return states;
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}
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static void
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static void
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radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
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radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *pCreateInfo)
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const VkGraphicsPipelineCreateInfo *pCreateInfo)
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{
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{
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uint32_t states = RADV_DYNAMIC_ALL;
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uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
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uint32_t states = needed_states;
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RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
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RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
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struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
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struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
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pipeline->dynamic_state = default_dynamic_state;
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pipeline->dynamic_state = default_dynamic_state;
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pipeline->graphics.needed_dynamic_state = needed_states;
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if (pCreateInfo->pDynamicState) {
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if (pCreateInfo->pDynamicState) {
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/* Remove all of the states that are marked as dynamic */
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/* Remove all of the states that are marked as dynamic */
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@ -1050,26 +1083,23 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
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struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
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struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
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/* Section 9.2 of the Vulkan 1.0.15 spec says:
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if (needed_states & RADV_DYNAMIC_VIEWPORT) {
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*
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* pViewportState is [...] NULL if the pipeline
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* has rasterization disabled.
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*/
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if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
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assert(pCreateInfo->pViewportState);
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assert(pCreateInfo->pViewportState);
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dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
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dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
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if (states & RADV_DYNAMIC_VIEWPORT) {
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if (states & RADV_DYNAMIC_VIEWPORT) {
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typed_memcpy(dynamic->viewport.viewports,
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typed_memcpy(dynamic->viewport.viewports,
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pCreateInfo->pViewportState->pViewports,
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pCreateInfo->pViewportState->pViewports,
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pCreateInfo->pViewportState->viewportCount);
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pCreateInfo->pViewportState->viewportCount);
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}
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}
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}
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if (needed_states & RADV_DYNAMIC_SCISSOR) {
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dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
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dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
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if (states & RADV_DYNAMIC_SCISSOR) {
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if (states & RADV_DYNAMIC_SCISSOR) {
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typed_memcpy(dynamic->scissor.scissors,
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typed_memcpy(dynamic->scissor.scissors,
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pCreateInfo->pViewportState->pScissors,
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pCreateInfo->pViewportState->pScissors,
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pCreateInfo->pViewportState->scissorCount);
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pCreateInfo->pViewportState->scissorCount);
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}
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}
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}
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}
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@ -1120,7 +1150,7 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
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* disabled or if the subpass of the render pass the pipeline is created
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* disabled or if the subpass of the render pass the pipeline is created
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* against does not use a depth/stencil attachment.
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* against does not use a depth/stencil attachment.
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*/
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*/
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if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
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if (needed_states &&
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subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
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subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
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assert(pCreateInfo->pDepthStencilState);
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assert(pCreateInfo->pDepthStencilState);
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@ -1155,7 +1185,7 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
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const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
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const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
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vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
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vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
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if (discard_rectangle_info) {
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if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
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dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
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dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
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typed_memcpy(dynamic->discard_rectangle.rectangles,
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typed_memcpy(dynamic->discard_rectangle.rectangles,
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discard_rectangle_info->pDiscardRectangles,
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discard_rectangle_info->pDiscardRectangles,
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@ -1181,8 +1211,6 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
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}
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}
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pipeline->graphics.pa_sc_cliprect_rule = mask;
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pipeline->graphics.pa_sc_cliprect_rule = mask;
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} else {
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} else {
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states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
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/* Allow from all rectangle combinations */
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/* Allow from all rectangle combinations */
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pipeline->graphics.pa_sc_cliprect_rule = 0xffff;
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pipeline->graphics.pa_sc_cliprect_rule = 0xffff;
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}
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}
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@ -2441,7 +2469,6 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
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pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
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pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
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assert(pipeline->layout);
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assert(pipeline->layout);
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radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
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radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
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radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
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const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
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const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
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@ -2476,6 +2503,8 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
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/* prim vertex count will need TESS changes */
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/* prim vertex count will need TESS changes */
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pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
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pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
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radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
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/* Ensure that some export memory is always allocated, for two reasons:
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/* Ensure that some export memory is always allocated, for two reasons:
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*
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*
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* 1) Correctness: The hardware ignores the EXEC mask if no export
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* 1) Correctness: The hardware ignores the EXEC mask if no export
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@ -1262,6 +1262,7 @@ struct radv_pipeline {
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struct radv_prim_vertex_count prim_vertex_count;
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struct radv_prim_vertex_count prim_vertex_count;
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bool can_use_guardband;
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bool can_use_guardband;
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uint32_t pa_sc_cliprect_rule;
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uint32_t pa_sc_cliprect_rule;
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uint32_t needed_dynamic_state;
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} graphics;
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} graphics;
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};
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};
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