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radv: update the HTILE clear word when VRS is used 

SR1 is the VRS x-rate.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
This commit is contained in:
Samuel Pitoiset 2021-03-22 18:15:26 +01:00 committed by Marge Bot
parent d075711b0e
commit 7bd3a9f502
2 changed files with 16 additions and 2 deletions
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6
src/amd/vulkan/radv_meta_clear.c
View File

@ -873,7 +873,11 @@ radv_get_htile_fast_clear_value(const struct radv_device *device, const struct r
if (radv_image_tile_stencil_disabled(device, image)) {
clear_value = value.depth ? 0xfffffff0 : 0;
} else {
clear_value = value.depth ? 0xfffc00f0 : 0xf0;
if (radv_image_has_vrs_htile(device, image))
clear_value = value.depth ? 0xfffc0030 : 0x30;
else {
clear_value = value.depth ? 0xfffc00f0 : 0xf0;
}
}
return clear_value;

12
src/amd/vulkan/radv_private.h
View File

@ -2045,8 +2045,18 @@ radv_get_htile_initial_value(const struct radv_device *device, const struct radv
*
* SR0/SR1 contains the stencil test results. Initializing
* SR0/SR1 to 0x3 means the stencil test result is unknown.
*
* Z, stencil and 4 bit VRS encoding:
* |31 12|11 10|9 8|7 6|5 4|3 0|
* +-----------+------------+------+------------+-----+-------+
* | Z Range | VRS y-rate | SMem | VRS x-rate | SR0 | ZMask |
*/
initial_value = 0xfffff3ff;
if (radv_image_has_vrs_htile(device, image)) {
/* Initialize the VRS x-rate value at 0, so the hw interprets it as 1 sample. */
initial_value = 0xfffff33f;
} else {
initial_value = 0xfffff3ff;
}
}
return initial_value;