radeonsi/gfx10: implement gfx10_emit_cache_flush
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
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0c6c6810bd
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7bb9bb0540
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@ -487,7 +487,11 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
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goto fail;
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/* Initialize context functions used by graphics and compute. */
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sctx->emit_cache_flush = si_emit_cache_flush;
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if (sctx->chip_class >= GFX10)
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sctx->emit_cache_flush = gfx10_emit_cache_flush;
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else
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sctx->emit_cache_flush = si_emit_cache_flush;
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sctx->b.emit_string_marker = si_emit_string_marker;
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sctx->b.set_debug_callback = si_set_debug_callback;
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sctx->b.set_log_context = si_set_log_context;
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@ -65,9 +65,11 @@
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#define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
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/* Instruction cache. */
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#define SI_CONTEXT_INV_ICACHE (1 << 3)
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/* Scalar L1 cache. */
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/* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
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* GFX10: This also invalidates the L1 shader array cache. */
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#define SI_CONTEXT_INV_SCACHE (1 << 4)
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/* Vector L1 cache. */
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/* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
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* GFX10: This also invalidates the L1 shader array cache. */
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#define SI_CONTEXT_INV_VCACHE (1 << 5)
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/* L2 cache + L2 metadata cache writeback & invalidate.
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* GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
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@ -596,6 +596,7 @@ void si_shader_selector_key_vs(struct si_context *sctx,
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void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
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unsigned cp_coher_cntl);
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void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx);
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void gfx10_emit_cache_flush(struct si_context *sctx);
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void si_emit_cache_flush(struct si_context *sctx);
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void si_trace_emit(struct si_context *sctx);
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void si_init_draw_functions(struct si_context *sctx);
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@ -951,6 +951,191 @@ void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
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*sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
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}
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void gfx10_emit_cache_flush(struct si_context *ctx)
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{
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struct radeon_cmdbuf *cs = ctx->gfx_cs;
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uint32_t gcr_cntl = 0;
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unsigned cb_db_event = 0;
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unsigned flags = ctx->flags;
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if (!ctx->has_graphics) {
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/* Only process compute flags. */
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flags &= SI_CONTEXT_INV_ICACHE |
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SI_CONTEXT_INV_SCACHE |
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SI_CONTEXT_INV_VCACHE |
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SI_CONTEXT_INV_L2 |
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SI_CONTEXT_WB_L2 |
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SI_CONTEXT_INV_L2_METADATA |
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SI_CONTEXT_CS_PARTIAL_FLUSH;
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}
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/* We don't need these. */
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assert(!(flags & (SI_CONTEXT_VGT_FLUSH |
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SI_CONTEXT_VGT_STREAMOUT_SYNC |
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SI_CONTEXT_FLUSH_AND_INV_DB_META)));
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if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
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ctx->num_cb_cache_flushes++;
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if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
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ctx->num_db_cache_flushes++;
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if (flags & SI_CONTEXT_INV_ICACHE)
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gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
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if (flags & SI_CONTEXT_INV_SCACHE) {
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/* TODO: When writing to the SMEM L1 cache, we need to set SEQ
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* to FORWARD when both L1 and L2 are written out (WB or INV).
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*/
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gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
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}
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if (flags & SI_CONTEXT_INV_VCACHE)
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gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
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if (flags & SI_CONTEXT_INV_L2) {
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/* Writeback and invalidate everything in L2. */
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gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
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ctx->num_L2_invalidates++;
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} else if (flags & SI_CONTEXT_WB_L2) {
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/* Writeback but do not invalidate. */
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gcr_cntl |= S_586_GL2_WB(1);
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}
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if (flags & SI_CONTEXT_INV_L2_METADATA)
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gcr_cntl |= S_586_GLM_INV(1);
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if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
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if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
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/* Flush CMASK/FMASK/DCC. Will wait for idle later. */
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
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EVENT_INDEX(0));
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}
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if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
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/* Flush HTILE. Will wait for idle later. */
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
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EVENT_INDEX(0));
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}
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/* First flush CB/DB, then L1/L2. */
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gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
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if ((flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) ==
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(SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
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cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
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} else if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
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cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
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} else if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
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cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
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} else {
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assert(0);
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}
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} else {
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/* Wait for graphics shaders to go idle if requested. */
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if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
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/* Only count explicit shader flushes, not implicit ones. */
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ctx->num_vs_flushes++;
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ctx->num_ps_flushes++;
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} else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
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ctx->num_vs_flushes++;
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}
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}
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if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && ctx->compute_is_busy) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
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ctx->num_cs_flushes++;
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ctx->compute_is_busy = false;
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}
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if (cb_db_event) {
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/* CB/DB flush and invalidate (or possibly just a wait for a
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* meta flush) via RELEASE_MEM.
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*
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* Combine this with other cache flushes when possible; this
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* requires affected shaders to be idle, so do it after the
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* CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
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* implied).
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*/
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uint64_t va;
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/* Do the flush (enqueue the event and wait for it). */
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va = ctx->wait_mem_scratch->gpu_address;
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ctx->wait_mem_number++;
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/* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
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unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
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unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
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unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
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unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
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assert(G_586_GL2_US(gcr_cntl) == 0);
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assert(G_586_GL2_RANGE(gcr_cntl) == 0);
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assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
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unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
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unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
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unsigned gcr_seq = G_586_SEQ(gcr_cntl);
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gcr_cntl &= C_586_GLM_WB &
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C_586_GLM_INV &
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C_586_GLV_INV &
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C_586_GL1_INV &
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C_586_GL2_INV &
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C_586_GL2_WB; /* keep SEQ */
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si_cp_release_mem(ctx, cs, cb_db_event,
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S_490_GLM_WB(glm_wb) |
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S_490_GLM_INV(glm_inv) |
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S_490_GLV_INV(glv_inv) |
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S_490_GL1_INV(gl1_inv) |
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S_490_GL2_INV(gl2_inv) |
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S_490_GL2_WB(gl2_wb) |
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S_490_SEQ(gcr_seq),
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EOP_DST_SEL_MEM,
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EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
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EOP_DATA_SEL_VALUE_32BIT,
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ctx->wait_mem_scratch, va,
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ctx->wait_mem_number, SI_NOT_QUERY);
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si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff,
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WAIT_REG_MEM_EQUAL);
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}
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/* Ignore fields that only modify the behavior of other fields. */
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if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
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/* Flush caches and wait for the caches to assert idle.
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* The cache flush is executed in the ME, but the PFP waits
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* for completion.
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*/
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radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
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radeon_emit(cs, 0); /* CP_COHER_CNTL */
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radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
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radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
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radeon_emit(cs, 0); /* CP_COHER_BASE */
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radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
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radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
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radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
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} else if (cb_db_event ||
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(flags & (SI_CONTEXT_VS_PARTIAL_FLUSH |
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SI_CONTEXT_PS_PARTIAL_FLUSH |
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SI_CONTEXT_CS_PARTIAL_FLUSH))) {
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/* We need to ensure that PFP waits as well. */
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radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
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radeon_emit(cs, 0);
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}
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if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
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EVENT_INDEX(0));
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} else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
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EVENT_INDEX(0));
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}
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ctx->flags = 0;
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}
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void si_emit_cache_flush(struct si_context *sctx)
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{
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struct radeon_cmdbuf *cs = sctx->gfx_cs;
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