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radv: Support task shaders in secondary cmd buffers. 

Special consideration is needed to keep ACE and GFX in sync.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16531>
This commit is contained in:
Timur Kristóf 2022-02-12 21:30:55 +01:00 committed by Marge Bot
parent 4c6f83006d
commit 7b8f087f6b
1 changed files with 33 additions and 0 deletions
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33
src/amd/vulkan/radv_cmd_buffer.c
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@ -6187,6 +6187,39 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
radv_emit_framebuffer_state(primary);
}
if (secondary->ace_internal.cs) {
if (!primary->ace_internal.cs) {
primary->ace_internal.cs = radv_ace_internal_create(primary);
if (!primary->ace_internal.cs)
return;
}
struct radeon_cmdbuf *ace_primary = primary->ace_internal.cs;
struct radeon_cmdbuf *ace_secondary = secondary->ace_internal.cs;
/* Emit pending flushes on primary prior to executing secondary. */
radv_ace_internal_cache_flush(primary);
/* Wait for primary GFX->ACE semaphore, if necessary. */
if (radv_flush_gfx2ace_semaphore(primary))
radv_wait_gfx2ace_semaphore(primary);
/* Execute the secondary compute cmdbuf.
* Don't use IB2 packets because they are not supported on compute queues.
*/
primary->device->ws->cs_execute_secondary(ace_primary, ace_secondary, false);
}
/* Update pending ACE internal flush bits from the secondary cmdbuf */
primary->ace_internal.flush_bits |= secondary->ace_internal.flush_bits;
/* Increment primary semaphore if secondary was dirty.
* This happens when the secondary cmdbuf has a barrier which
* isn't consumed by a draw call.
*/
if (radv_ace_internal_sem_dirty(secondary))
primary->ace_internal.sem.gfx2ace_value++;
primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs, allow_ib2);
/* When the secondary command buffer is compute only we don't