From 7b4eb731f1d819d4fdaa31fa1a736cdcd31a8818 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Sat, 24 Jul 2021 13:01:08 -0400 Subject: [PATCH] asahi: Use agx_rsrc_offset for linear transfer_map Signed-off-by: Alyssa Rosenzweig Part-of: --- src/gallium/drivers/asahi/agx_pipe.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/asahi/agx_pipe.c b/src/gallium/drivers/asahi/agx_pipe.c index ec15e470a5e..e5cd92663d9 100644 --- a/src/gallium/drivers/asahi/agx_pipe.c +++ b/src/gallium/drivers/asahi/agx_pipe.c @@ -293,7 +293,6 @@ agx_transfer_map(struct pipe_context *pctx, struct agx_context *ctx = agx_context(pctx); struct agx_resource *rsrc = agx_resource(resource); unsigned bytes_per_pixel = util_format_get_blocksize(resource->format); - struct agx_bo *bo = rsrc->bo; /* Can't map tiled/compressed directly */ if ((usage & PIPE_MAP_DIRECTLY) && rsrc->modifier != DRM_FORMAT_MOD_LINEAR) @@ -334,16 +333,14 @@ agx_transfer_map(struct pipe_context *pctx, assert (rsrc->modifier == DRM_FORMAT_MOD_LINEAR); transfer->base.stride = rsrc->slices[level].line_stride; - transfer->base.layer_stride = 0; // TODO + transfer->base.layer_stride = rsrc->array_stride; /* Be conservative for direct writes */ if ((usage & PIPE_MAP_WRITE) && (usage & PIPE_MAP_DIRECTLY)) BITSET_SET(rsrc->data_valid, level); - return ((uint8_t *) bo->ptr.cpu) - + rsrc->slices[level].offset - + transfer->base.box.z * transfer->base.layer_stride + return agx_rsrc_offset(rsrc, level, box->z) + transfer->base.box.y * rsrc->slices[level].line_stride + transfer->base.box.x * bytes_per_pixel; }