radeonsi: ubo indexing support (v2)
This is required as part of ARB_gpu_shader5. no backend changes are required for this, or if any are, it's the same ones as for samplers. v2: use get_indirect_index (Marek) Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
b0654e368b
commit
7b40d92f0d
|
@ -99,7 +99,7 @@ GL 4.0, GLSL 4.00:
|
||||||
GL_ARB_gpu_shader5 DONE (i965, nvc0)
|
GL_ARB_gpu_shader5 DONE (i965, nvc0)
|
||||||
- 'precise' qualifier DONE
|
- 'precise' qualifier DONE
|
||||||
- Dynamically uniform sampler array indices DONE (r600, radeonsi, softpipe)
|
- Dynamically uniform sampler array indices DONE (r600, radeonsi, softpipe)
|
||||||
- Dynamically uniform UBO array indices DONE (r600)
|
- Dynamically uniform UBO array indices DONE (r600, radeonsi)
|
||||||
- Implicit signed -> unsigned conversions DONE
|
- Implicit signed -> unsigned conversions DONE
|
||||||
- Fused multiply-add DONE ()
|
- Fused multiply-add DONE ()
|
||||||
- Packing/bitfield/conversion functions DONE (r600, radeonsi, softpipe)
|
- Packing/bitfield/conversion functions DONE (r600, radeonsi, softpipe)
|
||||||
|
|
|
@ -1191,7 +1191,7 @@ static LLVMValueRef fetch_constant(
|
||||||
const struct tgsi_ind_register *ireg = ®->Indirect;
|
const struct tgsi_ind_register *ireg = ®->Indirect;
|
||||||
unsigned buf, idx;
|
unsigned buf, idx;
|
||||||
|
|
||||||
LLVMValueRef addr;
|
LLVMValueRef addr, bufp;
|
||||||
LLVMValueRef result;
|
LLVMValueRef result;
|
||||||
|
|
||||||
if (swizzle == LP_CHAN_ALL) {
|
if (swizzle == LP_CHAN_ALL) {
|
||||||
|
@ -1206,7 +1206,7 @@ static LLVMValueRef fetch_constant(
|
||||||
buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
|
buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
|
||||||
idx = reg->Register.Index * 4 + swizzle;
|
idx = reg->Register.Index * 4 + swizzle;
|
||||||
|
|
||||||
if (!reg->Register.Indirect) {
|
if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
|
||||||
if (type != TGSI_TYPE_DOUBLE)
|
if (type != TGSI_TYPE_DOUBLE)
|
||||||
return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
|
return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
|
||||||
else {
|
else {
|
||||||
|
@ -1216,13 +1216,22 @@ static LLVMValueRef fetch_constant(
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (reg->Register.Dimension && reg->Dimension.Indirect) {
|
||||||
|
LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
|
||||||
|
LLVMValueRef index;
|
||||||
|
index = get_indirect_index(si_shader_ctx, ®->DimIndirect,
|
||||||
|
reg->Dimension.Index);
|
||||||
|
bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
|
||||||
|
} else
|
||||||
|
bufp = si_shader_ctx->const_resource[buf];
|
||||||
|
|
||||||
addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
|
addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
|
||||||
addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
|
addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
|
||||||
addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
|
addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
|
||||||
addr = lp_build_add(&bld_base->uint_bld, addr,
|
addr = lp_build_add(&bld_base->uint_bld, addr,
|
||||||
lp_build_const_int32(base->gallivm, idx * 4));
|
lp_build_const_int32(base->gallivm, idx * 4));
|
||||||
|
|
||||||
result = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
|
result = buffer_load_const(base->gallivm->builder, bufp,
|
||||||
addr, bld_base->base.elem_type);
|
addr, bld_base->base.elem_type);
|
||||||
|
|
||||||
if (type != TGSI_TYPE_DOUBLE)
|
if (type != TGSI_TYPE_DOUBLE)
|
||||||
|
|
Loading…
Reference in New Issue