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radeonsi: ubo indexing support (v2) 

This is required as part of ARB_gpu_shader5.

no backend changes are required for this, or if
any are, it's the same ones as for samplers.

v2: use get_indirect_index (Marek)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2015-07-13 09:12:18 +01:00
parent b0654e368b
commit 7b40d92f0d
2 changed files with 13 additions and 4 deletions
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2
docs/GL3.txt
View File

@ -99,7 +99,7 @@ GL 4.0, GLSL 4.00:
GL_ARB_gpu_shader5 DONE (i965, nvc0)
- 'precise' qualifier DONE
- Dynamically uniform sampler array indices DONE (r600, radeonsi, softpipe)
- Dynamically uniform UBO array indices DONE (r600)
- Dynamically uniform UBO array indices DONE (r600, radeonsi)
- Implicit signed -> unsigned conversions DONE
- Fused multiply-add DONE ()
- Packing/bitfield/conversion functions DONE (r600, radeonsi, softpipe)

15
src/gallium/drivers/radeonsi/si_shader.c
View File

@ -1191,7 +1191,7 @@ static LLVMValueRef fetch_constant(
const struct tgsi_ind_register *ireg = &reg->Indirect;
unsigned buf, idx;
LLVMValueRef addr;
LLVMValueRef addr, bufp;
LLVMValueRef result;
if (swizzle == LP_CHAN_ALL) {
@ -1206,7 +1206,7 @@ static LLVMValueRef fetch_constant(
buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
idx = reg->Register.Index * 4 + swizzle;
if (!reg->Register.Indirect) {
if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
if (type != TGSI_TYPE_DOUBLE)
return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
else {
@ -1216,13 +1216,22 @@ static LLVMValueRef fetch_constant(
}
}
if (reg->Register.Dimension && reg->Dimension.Indirect) {
LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
LLVMValueRef index;
index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
reg->Dimension.Index);
bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
} else
bufp = si_shader_ctx->const_resource[buf];
addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
addr = lp_build_add(&bld_base->uint_bld, addr,
lp_build_const_int32(base->gallivm, idx * 4));
result = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
result = buffer_load_const(base->gallivm->builder, bufp,
addr, bld_base->base.elem_type);
if (type != TGSI_TYPE_DOUBLE)