radeonsi: put image, fmask, and sampler descriptors into one array
The texture slot is expanded to 16 dwords containing 2 descriptors. Those can be: - Image and fmask, or - Image and sampler state By carefully choosing the locations, we can put all three into one slot, with the fmask and sampler state being mutually exclusive. This improves shaders in 2 ways: - 2 user SGPRs are unused, shaders can use them as temporary registers now - each pair of descriptors is always on the same cache line v2: cosmetic changes: add back v8i32, don't load a sampler state & fmask at the same time Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
parent
796ee76e2e
commit
7aedbbacae
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@ -80,7 +80,7 @@ static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
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if (op & SI_SAVE_TEXTURES) {
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util_blitter_save_fragment_sampler_states(
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sctx->blitter, 2,
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sctx->samplers[PIPE_SHADER_FRAGMENT].states.saved_states);
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sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
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util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
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sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
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@ -41,6 +41,18 @@
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*
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* Also, uploading descriptors to newly allocated memory doesn't require
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* a KCACHE flush.
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*
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*
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* Possible scenarios for one 16 dword image+sampler slot:
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*
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* | Image | w/ FMASK | Buffer | NULL
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* [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
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* [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
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* [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
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* [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
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*
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* FMASK implies MSAA, therefore no sampler state.
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* Sampler states are never unbound except when FMASK is bound.
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*/
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#include "radeon/r600_cs.h"
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@ -88,9 +100,9 @@ static void si_init_descriptors(struct si_descriptors *desc,
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desc->shader_userdata_offset = shader_userdata_index * 4;
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/* Initialize the array to NULL descriptors if the element size is 8. */
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if (element_dw_size == 8)
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for (i = 0; i < num_elements; i++)
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memcpy(desc->list + i*element_dw_size, null_descriptor,
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if (element_dw_size % 8 == 0)
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for (i = 0; i < num_elements * element_dw_size / 8; i++)
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memcpy(desc->list + i*8, null_descriptor,
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sizeof(null_descriptor));
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}
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@ -174,27 +186,42 @@ static void si_sampler_views_begin_new_cs(struct si_context *sctx,
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RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
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}
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static void si_set_sampler_view(struct si_context *sctx, unsigned shader,
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unsigned slot, struct pipe_sampler_view *view,
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unsigned *view_desc)
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static void si_set_sampler_view(struct si_context *sctx,
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struct si_sampler_views *views,
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unsigned slot, struct pipe_sampler_view *view)
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{
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struct si_sampler_views *views = &sctx->samplers[shader].views;
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if (views->views[slot] == view)
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return;
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if (view) {
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struct si_sampler_view *rview =
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(struct si_sampler_view*)view;
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struct r600_texture *rtex = (struct r600_texture*)view->texture;
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si_sampler_view_add_buffers(sctx, rview);
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pipe_sampler_view_reference(&views->views[slot], view);
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memcpy(views->desc.list + slot*8, view_desc, 8*4);
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memcpy(views->desc.list + slot * 16, rview->state, 8*4);
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if (rtex && rtex->fmask.size) {
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memcpy(views->desc.list + slot*16 + 8,
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rview->fmask_state, 8*4);
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} else {
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/* Disable FMASK and bind sampler state in [12:15]. */
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memcpy(views->desc.list + slot*16 + 8,
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null_descriptor, 4*4);
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if (views->sampler_states[slot])
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memcpy(views->desc.list + slot*16 + 12,
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views->sampler_states[slot], 4*4);
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}
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views->desc.enabled_mask |= 1llu << slot;
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} else {
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pipe_sampler_view_reference(&views->views[slot], NULL);
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memcpy(views->desc.list + slot*8, null_descriptor, 8*4);
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memcpy(views->desc.list + slot*16, null_descriptor, 8*4);
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/* Only clear the lower dwords of FMASK. */
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memcpy(views->desc.list + slot*16 + 8, null_descriptor, 4*4);
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views->desc.enabled_mask &= ~(1llu << slot);
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}
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@ -208,7 +235,6 @@ static void si_set_sampler_views(struct pipe_context *ctx,
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_textures_info *samplers = &sctx->samplers[shader];
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struct si_sampler_view **rviews = (struct si_sampler_view **)views;
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int i;
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if (!count || shader >= SI_NUM_SHADERS)
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@ -220,13 +246,11 @@ static void si_set_sampler_views(struct pipe_context *ctx,
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if (!views || !views[i]) {
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samplers->depth_texture_mask &= ~(1 << slot);
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samplers->compressed_colortex_mask &= ~(1 << slot);
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si_set_sampler_view(sctx, shader, slot, NULL, NULL);
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si_set_sampler_view(sctx, shader, SI_FMASK_TEX_OFFSET + slot,
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NULL, NULL);
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si_set_sampler_view(sctx, &samplers->views, slot, NULL);
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continue;
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}
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si_set_sampler_view(sctx, shader, slot, views[i], rviews[i]->state);
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si_set_sampler_view(sctx, &samplers->views, slot, views[i]);
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if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
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struct r600_texture *rtex =
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@ -243,60 +267,46 @@ static void si_set_sampler_views(struct pipe_context *ctx,
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} else {
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samplers->compressed_colortex_mask &= ~(1 << slot);
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}
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if (rtex->fmask.size) {
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si_set_sampler_view(sctx, shader, SI_FMASK_TEX_OFFSET + slot,
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views[i], rviews[i]->fmask_state);
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} else {
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si_set_sampler_view(sctx, shader, SI_FMASK_TEX_OFFSET + slot,
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NULL, NULL);
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}
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} else {
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samplers->depth_texture_mask &= ~(1 << slot);
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samplers->compressed_colortex_mask &= ~(1 << slot);
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si_set_sampler_view(sctx, shader, SI_FMASK_TEX_OFFSET + slot,
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NULL, NULL);
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}
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}
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}
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/* SAMPLER STATES */
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static void si_sampler_states_begin_new_cs(struct si_context *sctx,
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struct si_sampler_states *states)
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{
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if (!states->desc.buffer)
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return;
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, states->desc.buffer,
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RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
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}
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static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
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unsigned start, unsigned count, void **states)
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_sampler_states *samplers = &sctx->samplers[shader].states;
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struct si_textures_info *samplers = &sctx->samplers[shader];
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struct si_descriptors *desc = &samplers->views.desc;
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struct si_sampler_state **sstates = (struct si_sampler_state**)states;
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int i;
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if (!count || shader >= SI_NUM_SHADERS)
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return;
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if (start == 0)
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samplers->saved_states[0] = states[0];
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if (start == 1)
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samplers->saved_states[1] = states[0];
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else if (start == 0 && count >= 2)
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samplers->saved_states[1] = states[1];
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for (i = 0; i < count; i++) {
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unsigned slot = start + i;
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if (!sstates[i])
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if (!sstates[i] ||
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sstates[i] == samplers->views.sampler_states[slot])
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continue;
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memcpy(samplers->desc.list + slot*4, sstates[i]->val, 4*4);
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samplers->desc.list_dirty = true;
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samplers->views.sampler_states[slot] = sstates[i];
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/* If FMASK is bound, don't overwrite it.
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* The sampler state will be set after FMASK is unbound.
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*/
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if (samplers->views.views[i] &&
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samplers->views.views[i]->texture &&
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((struct r600_texture*)samplers->views.views[i]->texture)->fmask.size)
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continue;
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memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
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desc->list_dirty = true;
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}
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}
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@ -862,7 +872,9 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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while (mask) {
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unsigned i = u_bit_scan64(&mask);
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if (views->views[i]->texture == buf) {
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si_desc_reset_buffer_offset(ctx, views->desc.list + i*8+4,
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si_desc_reset_buffer_offset(ctx,
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views->desc.list +
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i * 16 + 4,
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old_va, buf);
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views->desc.list_dirty = true;
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@ -882,7 +894,6 @@ static void si_mark_shader_pointers_dirty(struct si_context *sctx,
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sctx->const_buffers[shader].desc.pointer_dirty = true;
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sctx->rw_buffers[shader].desc.pointer_dirty = true;
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sctx->samplers[shader].views.desc.pointer_dirty = true;
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sctx->samplers[shader].states.desc.pointer_dirty = true;
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if (shader == PIPE_SHADER_VERTEX)
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sctx->vertex_buffers.pointer_dirty = true;
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@ -1003,7 +1014,6 @@ void si_emit_shader_userdata(struct si_context *sctx, struct r600_atom *atom)
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si_emit_shader_pointer(sctx, &sctx->const_buffers[i].desc, base, false);
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si_emit_shader_pointer(sctx, &sctx->samplers[i].views.desc, base, false);
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si_emit_shader_pointer(sctx, &sctx->samplers[i].states.desc, base, false);
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}
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si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
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}
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@ -1023,9 +1033,7 @@ void si_init_all_descriptors(struct si_context *sctx)
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RADEON_USAGE_READWRITE, RADEON_PRIO_RINGS_STREAMOUT);
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si_init_descriptors(&sctx->samplers[i].views.desc,
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SI_SGPR_SAMPLER_VIEWS, 8, SI_NUM_SAMPLER_VIEWS);
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si_init_descriptors(&sctx->samplers[i].states.desc,
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SI_SGPR_SAMPLER_STATES, 4, SI_NUM_SAMPLER_STATES);
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SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS);
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}
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si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
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@ -1056,8 +1064,7 @@ bool si_upload_shader_descriptors(struct si_context *sctx)
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for (i = 0; i < SI_NUM_SHADERS; i++) {
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if (!si_upload_descriptors(sctx, &sctx->const_buffers[i].desc) ||
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!si_upload_descriptors(sctx, &sctx->rw_buffers[i].desc) ||
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!si_upload_descriptors(sctx, &sctx->samplers[i].views.desc) ||
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!si_upload_descriptors(sctx, &sctx->samplers[i].states.desc))
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!si_upload_descriptors(sctx, &sctx->samplers[i].views.desc))
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return false;
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}
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return si_upload_vertex_buffer_descriptors(sctx);
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@ -1071,7 +1078,6 @@ void si_release_all_descriptors(struct si_context *sctx)
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si_release_buffer_resources(&sctx->const_buffers[i]);
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si_release_buffer_resources(&sctx->rw_buffers[i]);
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si_release_sampler_views(&sctx->samplers[i].views);
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si_release_descriptors(&sctx->samplers[i].states.desc);
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}
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si_release_descriptors(&sctx->vertex_buffers);
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}
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@ -1084,7 +1090,6 @@ void si_all_descriptors_begin_new_cs(struct si_context *sctx)
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si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
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si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers[i]);
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si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
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si_sampler_states_begin_new_cs(sctx, &sctx->samplers[i].states);
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}
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si_vertex_buffers_begin_new_cs(sctx);
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si_shader_userdata_begin_new_cs(sctx);
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@ -113,7 +113,6 @@ struct si_cs_shader_state {
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struct si_textures_info {
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struct si_sampler_views views;
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struct si_sampler_states states;
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uint32_t depth_texture_mask; /* which textures are depth */
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uint32_t compressed_colortex_mask;
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};
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@ -86,8 +86,9 @@ struct si_shader_context
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LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
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LLVMValueRef lds;
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LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
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LLVMValueRef sampler_views[SI_NUM_SAMPLER_VIEWS];
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LLVMValueRef sampler_states[SI_NUM_SAMPLER_STATES];
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LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
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LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
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LLVMValueRef fmasks[SI_NUM_USER_SAMPLERS];
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LLVMValueRef so_buffers[4];
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LLVMValueRef esgs_ring;
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LLVMValueRef gsvs_ring[4];
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@ -2480,13 +2481,58 @@ static void set_tex_fetch_args(struct gallivm_state *gallivm,
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static const struct lp_build_tgsi_action tex_action;
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enum desc_type {
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DESC_IMAGE,
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DESC_FMASK,
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DESC_SAMPLER
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};
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static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
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{
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return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
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CONST_ADDR_SPACE);
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}
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/**
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* Load an image view, fmask view. or sampler state descriptor.
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*/
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static LLVMValueRef get_sampler_desc(struct si_shader_context *si_shader_ctx,
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LLVMValueRef index, enum desc_type type)
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{
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struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
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LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
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LLVMBuilderRef builder = gallivm->builder;
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LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
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SI_PARAM_SAMPLERS);
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switch (type) {
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case DESC_IMAGE:
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/* The image is at [0:7]. */
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index = LLVMBuildMul(builder, index, LLVMConstInt(i32, 2, 0), "");
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break;
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case DESC_FMASK:
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/* The FMASK is at [8:15]. */
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index = LLVMBuildMul(builder, index, LLVMConstInt(i32, 2, 0), "");
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index = LLVMBuildAdd(builder, index, LLVMConstInt(i32, 1, 0), "");
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break;
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case DESC_SAMPLER:
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/* The sampler state is at [12:15]. */
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index = LLVMBuildMul(builder, index, LLVMConstInt(i32, 4, 0), "");
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index = LLVMBuildAdd(builder, index, LLVMConstInt(i32, 3, 0), "");
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ptr = LLVMBuildPointerCast(builder, ptr,
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const_array(LLVMVectorType(i32, 4), 0), "");
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break;
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}
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return build_indexed_load_const(si_shader_ctx, ptr, index);
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}
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static void tex_fetch_ptrs(
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struct lp_build_tgsi_context * bld_base,
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struct lp_build_emit_data * emit_data,
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LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
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{
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struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
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struct gallivm_state *gallivm = bld_base->base.gallivm;
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const struct tgsi_full_instruction * inst = emit_data->inst;
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unsigned target = inst->Texture.Texture;
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unsigned sampler_src;
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@ -2501,24 +2547,20 @@ static void tex_fetch_ptrs(
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ind_index = get_indirect_index(si_shader_ctx, ®->Indirect, reg->Register.Index);
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*res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
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*res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
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*samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
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*samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
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*res_ptr = get_sampler_desc(si_shader_ctx, ind_index, DESC_IMAGE);
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if (target == TGSI_TEXTURE_2D_MSAA ||
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target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
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ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
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lp_build_const_int32(gallivm,
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SI_FMASK_TEX_OFFSET), "");
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*fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
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*fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
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*samp_ptr = NULL;
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*fmask_ptr = get_sampler_desc(si_shader_ctx, ind_index, DESC_FMASK);
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} else {
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*samp_ptr = get_sampler_desc(si_shader_ctx, ind_index, DESC_SAMPLER);
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*fmask_ptr = NULL;
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}
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} else {
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*res_ptr = si_shader_ctx->sampler_views[sampler_index];
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*samp_ptr = si_shader_ctx->sampler_states[sampler_index];
|
||||
*fmask_ptr = si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + sampler_index];
|
||||
*fmask_ptr = si_shader_ctx->fmasks[sampler_index];
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -3498,12 +3540,6 @@ static void create_meta_data(struct si_shader_context *si_shader_ctx)
|
|||
si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
|
||||
}
|
||||
|
||||
static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
|
||||
{
|
||||
return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
|
||||
CONST_ADDR_SPACE);
|
||||
}
|
||||
|
||||
static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
|
||||
struct pipe_stream_output_info *so,
|
||||
LLVMTypeRef *params, LLVMTypeRef i32,
|
||||
|
@ -3530,7 +3566,7 @@ static void create_function(struct si_shader_context *si_shader_ctx)
|
|||
struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
|
||||
struct gallivm_state *gallivm = bld_base->base.gallivm;
|
||||
struct si_shader *shader = si_shader_ctx->shader;
|
||||
LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
|
||||
LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v8i32;
|
||||
unsigned i, last_array_pointer, last_sgpr, num_params;
|
||||
|
||||
i8 = LLVMInt8TypeInContext(gallivm->context);
|
||||
|
@ -3538,15 +3574,14 @@ static void create_function(struct si_shader_context *si_shader_ctx)
|
|||
f32 = LLVMFloatTypeInContext(gallivm->context);
|
||||
v2i32 = LLVMVectorType(i32, 2);
|
||||
v3i32 = LLVMVectorType(i32, 3);
|
||||
v4i32 = LLVMVectorType(i32, 4);
|
||||
v8i32 = LLVMVectorType(i32, 8);
|
||||
v16i8 = LLVMVectorType(i8, 16);
|
||||
|
||||
params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
|
||||
params[SI_PARAM_CONST_BUFFERS] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
|
||||
params[SI_PARAM_SAMPLER_STATES] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
|
||||
params[SI_PARAM_SAMPLER_VIEWS] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
|
||||
last_array_pointer = SI_PARAM_SAMPLER_VIEWS;
|
||||
params[SI_PARAM_SAMPLERS] = const_array(v8i32, SI_NUM_SAMPLERS);
|
||||
params[SI_PARAM_UNUSED] = LLVMPointerType(i32, CONST_ADDR_SPACE);
|
||||
last_array_pointer = SI_PARAM_UNUSED;
|
||||
|
||||
switch (si_shader_ctx->type) {
|
||||
case TGSI_PROCESSOR_VERTEX:
|
||||
|
@ -3747,34 +3782,26 @@ static void preload_samplers(struct si_shader_context *si_shader_ctx)
|
|||
struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
|
||||
struct gallivm_state * gallivm = bld_base->base.gallivm;
|
||||
const struct tgsi_shader_info * info = bld_base->info;
|
||||
|
||||
unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
|
||||
|
||||
LLVMValueRef res_ptr, samp_ptr;
|
||||
LLVMValueRef offset;
|
||||
|
||||
if (num_samplers == 0)
|
||||
return;
|
||||
|
||||
res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
|
||||
samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
|
||||
|
||||
/* Load the resources and samplers, we rely on the code sinking to do the rest */
|
||||
for (i = 0; i < num_samplers; ++i) {
|
||||
/* Resource */
|
||||
offset = lp_build_const_int32(gallivm, i);
|
||||
si_shader_ctx->sampler_views[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
|
||||
|
||||
/* Sampler */
|
||||
offset = lp_build_const_int32(gallivm, i);
|
||||
si_shader_ctx->sampler_states[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
|
||||
si_shader_ctx->sampler_views[i] =
|
||||
get_sampler_desc(si_shader_ctx, offset, DESC_IMAGE);
|
||||
|
||||
/* FMASK resource */
|
||||
if (info->is_msaa_sampler[i]) {
|
||||
offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
|
||||
si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + i] =
|
||||
build_indexed_load_const(si_shader_ctx, res_ptr, offset);
|
||||
}
|
||||
if (info->is_msaa_sampler[i])
|
||||
si_shader_ctx->fmasks[i] =
|
||||
get_sampler_desc(si_shader_ctx, offset, DESC_FMASK);
|
||||
else
|
||||
si_shader_ctx->sampler_states[i] =
|
||||
get_sampler_desc(si_shader_ctx, offset, DESC_SAMPLER);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -77,8 +77,8 @@ struct radeon_shader_reloc;
|
|||
|
||||
#define SI_SGPR_RW_BUFFERS 0 /* rings (& stream-out, VS only) */
|
||||
#define SI_SGPR_CONST_BUFFERS 2
|
||||
#define SI_SGPR_SAMPLER_STATES 4
|
||||
#define SI_SGPR_SAMPLER_VIEWS 6
|
||||
#define SI_SGPR_SAMPLERS 4 /* images & sampler states interleaved */
|
||||
/* TODO: gap */
|
||||
#define SI_SGPR_VERTEX_BUFFERS 8 /* VS only */
|
||||
#define SI_SGPR_BASE_VERTEX 10 /* VS only */
|
||||
#define SI_SGPR_START_INSTANCE 11 /* VS only */
|
||||
|
@ -101,8 +101,8 @@ struct radeon_shader_reloc;
|
|||
/* LLVM function parameter indices */
|
||||
#define SI_PARAM_RW_BUFFERS 0
|
||||
#define SI_PARAM_CONST_BUFFERS 1
|
||||
#define SI_PARAM_SAMPLER_STATES 2
|
||||
#define SI_PARAM_SAMPLER_VIEWS 3
|
||||
#define SI_PARAM_SAMPLERS 2
|
||||
#define SI_PARAM_UNUSED 3 /* TODO: use */
|
||||
|
||||
/* VS only parameters */
|
||||
#define SI_PARAM_VERTEX_BUFFERS 4
|
||||
|
|
|
@ -144,18 +144,13 @@ struct si_shader_data {
|
|||
uint32_t sh_base[SI_NUM_SHADERS];
|
||||
};
|
||||
|
||||
/* User sampler views: 0..15
|
||||
* Polygon stipple tex: 16
|
||||
*/
|
||||
#define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */
|
||||
#define SI_POLY_STIPPLE_SAMPLER SI_NUM_USER_SAMPLERS
|
||||
#define SI_NUM_SAMPLERS (SI_POLY_STIPPLE_SAMPLER + 1)
|
||||
|
||||
/* User sampler views: 0..15
|
||||
* Polygon stipple tex: 16
|
||||
* FMASK sampler views: 17..33 (no sampler states)
|
||||
*/
|
||||
#define SI_FMASK_TEX_OFFSET SI_NUM_SAMPLERS
|
||||
#define SI_NUM_SAMPLER_VIEWS (SI_FMASK_TEX_OFFSET + SI_NUM_SAMPLERS)
|
||||
#define SI_NUM_SAMPLER_STATES SI_NUM_SAMPLERS
|
||||
|
||||
/* User constant buffers: 0..15
|
||||
* Driver state constants: 16
|
||||
*/
|
||||
|
@ -210,12 +205,8 @@ struct si_descriptors {
|
|||
|
||||
struct si_sampler_views {
|
||||
struct si_descriptors desc;
|
||||
struct pipe_sampler_view *views[SI_NUM_SAMPLER_VIEWS];
|
||||
};
|
||||
|
||||
struct si_sampler_states {
|
||||
struct si_descriptors desc;
|
||||
void *saved_states[2]; /* saved for u_blitter */
|
||||
struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
|
||||
void *sampler_states[SI_NUM_SAMPLERS];
|
||||
};
|
||||
|
||||
struct si_buffer_resources {
|
||||
|
|
Loading…
Reference in New Issue