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radv: flush caches before performing separate depth/stencil aspect init 

It's a RMW operation, also note that DB doesn't use L2 on GFX6-8.

Fixes test_clear_depth_stencil_view() and test_discard_resource() tests
from vkd3d-proton.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12223>
This commit is contained in:
Samuel Pitoiset 2021-08-05 18:52:19 +02:00 committed by Marge Bot
parent 56fe30cbfc
commit 7ae3881a4b
1 changed files with 8 additions and 0 deletions
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8
src/amd/vulkan/radv_cmd_buffer.c
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@ -6624,6 +6624,14 @@ radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima
state->flush_bits |=
radv_src_access_flush(cmd_buffer, VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, image);
if (image->planes[0].surface.has_stencil &&
!(range->aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT))) {
/* Flush caches before performing a separate aspect initialization because it's a
* read-modify-write operation.
*/
state->flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_SHADER_READ_BIT, image);
}
state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
radv_set_ds_clear_metadata(cmd_buffer, image, range, value, range->aspectMask);