gallium/radeon: remove r600_htile_info
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
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7e73ff87c0
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7a706ad25c
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@ -240,14 +240,6 @@ struct r600_cmask_info {
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unsigned base_address_reg;
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};
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struct r600_htile_info {
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unsigned pitch;
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unsigned height;
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unsigned xalign;
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unsigned yalign;
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unsigned alignment;
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};
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struct r600_texture {
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struct r600_resource resource;
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@ -273,7 +265,6 @@ struct r600_texture {
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unsigned last_msaa_resolve_target_micro_mode;
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/* Depth buffer compression and fast clear. */
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struct r600_htile_info htile;
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struct r600_resource *htile_buffer;
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bool tc_compatible_htile;
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bool depth_cleared; /* if it was cleared at least once */
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@ -803,28 +803,30 @@ static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen
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p_atomic_inc(&rscreen->compressed_colortex_counter);
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}
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static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
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struct r600_texture *rtex)
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static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
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struct r600_texture *rtex)
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{
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unsigned cl_width, cl_height, width, height;
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unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
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unsigned num_pipes = rscreen->info.num_tile_pipes;
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rtex->surface.htile_size = 0;
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if (rscreen->chip_class <= EVERGREEN &&
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rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
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return 0;
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return;
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/* HW bug on R6xx. */
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if (rscreen->chip_class == R600 &&
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(rtex->resource.b.b.width0 > 7680 ||
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rtex->resource.b.b.height0 > 7680))
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return 0;
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return;
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/* HTILE is broken with 1D tiling on old kernels and CIK. */
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if (rscreen->chip_class >= CIK &&
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rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
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rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
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return 0;
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return;
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/* Overalign HTILE on P2 configs to work around GPU hangs in
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* piglit/depthstencil-render-miplevels 585.
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@ -859,7 +861,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
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break;
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default:
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assert(0);
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return 0;
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return;
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}
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width = align(rtex->resource.b.b.width0, cl_width * 8);
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@ -871,47 +873,40 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
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pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
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base_align = num_pipes * pipe_interleave_bytes;
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rtex->htile.pitch = width;
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rtex->htile.height = height;
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rtex->htile.xalign = cl_width * 8;
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rtex->htile.yalign = cl_height * 8;
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rtex->htile.alignment = base_align;
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return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
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rtex->surface.htile_alignment = base_align;
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rtex->surface.htile_size =
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(util_max_layer(&rtex->resource.b.b, 0) + 1) *
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align(slice_bytes, base_align);
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}
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static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
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struct r600_texture *rtex)
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{
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uint64_t htile_size, alignment;
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uint32_t clear_value;
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if (rtex->tc_compatible_htile) {
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htile_size = rtex->surface.htile_size;
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alignment = rtex->surface.htile_alignment;
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clear_value = 0x0000030F;
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} else {
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htile_size = r600_texture_get_htile_size(rscreen, rtex);
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alignment = rtex->htile.alignment;
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r600_texture_get_htile_size(rscreen, rtex);
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clear_value = 0;
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}
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if (!htile_size)
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if (!rtex->surface.htile_size)
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return;
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rtex->htile_buffer = (struct r600_resource*)
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r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
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PIPE_USAGE_DEFAULT,
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htile_size, alignment);
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r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
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PIPE_USAGE_DEFAULT,
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rtex->surface.htile_size,
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rtex->surface.htile_alignment);
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if (rtex->htile_buffer == NULL) {
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/* this is not a fatal error as we can still keep rendering
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* without htile buffer */
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R600_ERR("Failed to create buffer object for htile buffer.\n");
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} else {
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r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b,
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0, htile_size, clear_value,
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R600_COHERENCY_NONE);
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0, rtex->surface.htile_size,
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clear_value, R600_COHERENCY_NONE);
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}
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}
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@ -951,11 +946,9 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
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rtex->cmask.yalign, rtex->cmask.slice_tile_max);
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if (rtex->htile_buffer)
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fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
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"xalign=%u, yalign=%u, TC_compatible = %u\n",
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fprintf(f, " HTile: size=%u, alignment=%u, TC_compatible = %u\n",
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rtex->htile_buffer->b.b.width0,
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rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
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rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign,
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rtex->htile_buffer->buf->alignment,
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rtex->tc_compatible_htile);
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if (rtex->dcc_offset) {
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@ -327,7 +327,6 @@ struct radeon_surf {
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uint64_t dcc_size;
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uint32_t dcc_alignment;
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/* TC-compatible HTILE only. */
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uint64_t htile_size;
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uint32_t htile_alignment;
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};
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